COMP541 Flip-Flop Timing

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# COMP541 Flip-Flop Timing - PowerPoint PPT Presentation

COMP541 Flip-Flop Timing. Montek Singh Oct 6, 2014. Topics. Timing analysis flip - flops sequential systems clock skew. Lab 7 : VGA Display. Anyone having trouble with Lab 7? Be careful about the “Sync Polarity” A “1” means a downward going pulse

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### COMP541Flip-Flop Timing

Montek Singh

Oct 6, 2014

Topics
• Timing analysis
• flip-flops
• sequential systems
• clock skew
Lab 7: VGA Display
• Anyone having trouble with Lab 7?
• Be careful about the “Sync Polarity”
• A “1” means a downward going pulse
• sync signal is normally high, but goes low during the pulse
• A “0” means an upward going pulse
• Use my self-checking text bench!
• simulates my VGA driver …
• … and compares your outputs with mine
• flags any mismatches

### Timing of sequential circuits

Input Timing Constraints
• Setup time: tsetup = time before the clock edge that data must be stable (i.e. not changing)
• Hold time: thold = time after the clock edge that data must be stable
• Aperture time: ta = time around clock edge that data must be stable(ta = tsetup + thold)
Output Timing Constraints
• Propagation delay: tpcq= max time after clock edge by which output Q is guaranteed to have stabilized (i.e., not changing anymore)
• Contamination delay: tccq= min time after clock edge during which Q will not have started changing yet
Dynamic Discipline
• The input to a synchronous sequential circuit must be stable during the aperture (setup and hold) time around the clock edge
• Specifically, the input must be stable
• at least tsetup before the clock edge
• at least until thold after the clock edge
Implications on Design
• Constrains operation
• Given a clock period, constrains circuit delays
• Given a circuit, constraints clock period
• The delay between registers (which impacts clock period) has a minimum and maximum delay, dependent on the delays of the circuit elements
• Delays of both comb. logic and flip-flops must be taken into account
Setup Time Constraint
• Setup time
• input to R2 must be stable at least tsetup before the clock edge
• constrains max delay from R1 through combinational logic
• What’s min clock period?

What’s Tc?

Tc ≥ tpcq + tpd + tsetup

tpd ≤ Tc – (tpcq + tsetup)

• So, clock period constrained by:
• Delay in CL
• Delay in previous reg (R1)
• Setup requirement in next reg (R2)
Hold Time Constraint
• Hold time
• input to R2 must be stable for at least thold after clock edge
• constrains the minimum delay from register R1 through the combinational logic
• often try to design circuits with 0 hold time requirement

thold < tccq + tcd

tcd > thold - tccq

Timing Analysis

Timing Characteristics

tccq = 30 ps (FF contamination)

tpcq = 50 ps (FF propagation)

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 ps

tpd =

tcd =

Setup time constraint:

Tc≥

fc =

tpd = 3 x 35 ps = 105 ps

tcd = 25 ps

Setup time constraint:

Tc≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHz

Hold time constraint:

tccq + tcd > thold ?

(30 + 25) ps > 70 ps ? No!

Fixing Hold Time Violation

Add buffers to the short paths:

Timing Characteristics

tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 ps

tpd = 3 x 35 ps = 105 ps

tcd = 2 x 25 ps = 50 ps

Setup time constraint:

Tc≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHz

Hold time constraint:

tccq + tpd > thold ?

(30 + 50) ps > 70 ps ? Yes!

Hold Time
• Often flip-flops are designed for a hold time of zero
• To avoid these tricky problems
Clock Skew
• Clock doesn’t arrive at all registers at the same time
• Skew is the difference between the arrival times of the clock edge at two different (typically neighboring) flip-flops
• Examine the worst case:
• guarantee that discipline is not violated for anyregister pair
• many registers in a system!
Setup Time Constraint with Clock Skew

Worst case: CLK2 is earlier than CLK1

Tc ≥ tpcq + tpd + tsetup + tskew

tpd ≤ Tc – (tpcq + tsetup + tskew)

Similar Issue w/ Hold Time
• We won’t go over example
• Have a look in book
Next Time