1 / 7

GISMO Kickoff Meeting

GISMO Kickoff Meeting. Digital Receiver & Processing System. RSS iRAP System Overview. System Components. 3U Form Factor 8 / 12 Slot Configurations Conduction Cooled Network Processor (NPM) Switch Fabricate (SFM) 8 FPGA Processor Slots

tobit
Download Presentation

GISMO Kickoff Meeting

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. GISMO Kickoff Meeting Digital Receiver & Processing System

  2. RSS iRAP System Overview System Components • 3U Form Factor • 8 / 12 Slot Configurations • Conduction Cooled • Network Processor (NPM) • Switch Fabricate (SFM) • 8 FPGA Processor Slots • 2/4 Channel FPGA-based Digital Receiver (DARM) • FPGA-based Algorithm Processor (DARM) • FPGA-based Disk Striping CARD (DARM) • 3rd Party Cards • Ultra High Speed Communication Backplane (BRD) • Redundant Supplies GISMO Kickoff Meeting – 14 January 2009

  3. DARM: Digital Receiver Module • Digital Receiver Configuration • Virtex 5 SX95T FPGA processor. • ADC Mezzanine Card. • Supports up to 4 IF signals. • Supports up to 18 bit ADCs. • Multi-Channel Digital Receiver • Provides support for 2 or 4 IF channels. • Up to 8 / 4 sub channels per IF. • Independent NCO, bandwidth and match filter per sub channel. • Up to 200 MHz bandwidth per IF. • Pre-summing capability (18 bit resolution). • Sub channels reconfigurable on the fly. System Block Diagram GISMO Kickoff Meeting – 14 January 2009

  4. DARM: Digital Receiver (cont.) • Digital Receiver Data Bus • 10 Gb/s communications to NPM. • 6.4 Gb/s communications to each DARM • algorithm processor slot (up to four). • 6.4 Gb/s between adjacent receivers. • Supports PCIe communications. • Same card used as algorithm processor. • High Speed Digital Input Interface. • Conduction Cooled / High Altitude Operation System Block Diagram GISMO Kickoff Meeting – 14 January 2009

  5. Switch Fabric Module SWITCH BOARD Power Conditioning / Distribution JTAG XJ 1 VddCore = 1 . 0 VddPE = 1 . 0 VddAPE = 1 . 0 VttPE = 1 . 5 SMBUS XJ 4 EPROM Clock Refernce pair CLK 0 - 4 associated with each L PCIe Interface e PCIe 1 I x 2 XJ 4 [ 1 : 0 ] 2 CLK 1 / 2 NC [ 3 : 2 ] PCIe 2 x 2 XJ 4 [ 1 : 0 ] 3 NC CLK 2 / 2 EP 0 [ 3 : 2 ] REFCLK - PCIe 3 Clock Circuitry XJ 4 x 2 [ 1 : 0 ] 4 CLK 3 / 2 NC [ 3 : 2 ] PCIe 4 x 2 XJ 4 [ 1 : 0 ] 5 CLK 4 / 2 NC [ 3 : 2 ] PCIe 5 x 2 XJ 2 [ 1 : 0 ] 6 CLK 5 / 2 NC PCIe Switch [ 3 : 2 ] PCIe 6 XJ 2 x 2 [ 1 : 0 ] 7 CLK 6 / 2 NC [ 3 : 2 ] PCIe 7 x 2 XJ 2 [ 1 : 0 ] 8 CLK 7 / 2 NC [ 3 : 2 ] PCIe 8 x 2 XJ 2 [ 1 : 0 ] 9 - NC CLK 8 / 2 [ 3 : 2 ] PCIe 9 x 2 XJ 5 [ 1 : 0 ] 10 EP N - 1 NC [ 3 : 2 ] CLK 9 / 2 Clock Reference pair PCIe 10 associated with each UpStream x 2 XJ5 [ 1 : 0 ] 11 PCIe Interface NC CLK 10 / 2 [ 3 : 2 ] 0 1 [ 3 : 0 ] [ 3 : 0 ] PCIe 0 x 8 XJ 3 CLK 0 / 2 NPM CLK uPC XJ 3 • SFM Features: • Implements PCI Express switch. • 12 ports, 48 lanes • x8 Root Complex • Provides communication to / from • processor slots: • 5 Gb/s data rate both ways. • Expandable to 10 Gb/s. . • Provides bus clocks. • Standard bus to support 3rd party cards. • Conduction cooled design. • Supports high altitude operations. GISMO Kickoff Meeting – 14 January 2009

  6. Network Processor Module System Block Diagram • NPM Features: • Freescale MPC8548E Processor. • Supports: • 4 Gigabit Ethernet Engines. • x8 CompactPCIe Root Complex. • 4 SerDes (RocketIO). • I2C bus. • RS-232/RS-422. • Linux 2.6 Kernel. • Implements software layer • RSS System Object Language. • Conduction Cooled Design. • High Altitude Operations (70 Kft). Prototype / Development Board GISMO Kickoff Meeting – 14 January 2009

  7. GISMO Nominal Configuration • Four Digital Receiver Cards (DARM) • Three cards dedicated to interferometric radar. • Four IF channels per digital receiver. • 40-60 MHz bandwidth per IF channel. • Four channel 12-bit ADC mezzanine card. • One card dedicated to WISE. • DARM or 3rd Party Card • SATA striping solution. • Network Processor / SFM • Communication to other subsystems, communication systems and users. • Future Expansion / Trade Space • Support up to 20 interferometer channels plus WISE. • Single cage or dual cage solution. • Real-time sequential and/or parallel processing and storage. GISMO Kickoff Meeting – 14 January 2009

More Related