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August 2011 GR SEU measurements of FE-I4

August 2011 GR SEU measurements of FE-I4. A.Rozanov , 10.08.2011. August 2011 SEU measurements. Same two FE-I4-A Chip27and Chip28 installed in IRRAD3 proton beam PS CERN Beam available untill 15.09.2011

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August 2011 GR SEU measurements of FE-I4

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  1. August 2011GR SEU measurements of FE-I4 A.Rozanov, 10.08.2011

  2. August 2011 SEU measurements • Same two FE-I4-A Chip27and Chip28 installed in IRRAD3 proton beam PS CERN • Beam available untill 15.09.2011 • One interface board with defect IoMux driver exchanged, so now we can run IoMux on both chips • Mollex cables installed, so no more problems with voltage drops • RunMode implemented in STControl • Beam available from 4 August 2011, but lower density 20x10 mm or 15x10 mm (June 2011 approx 8x8 mm) and unstable shape • Reduction of flux density 2.9 • Increase in number of spills 4.6 • increase of SEU statistics factor 2.5

  3. Rates of GR errors in June • Assume PRDlike will be reduced and Efuse less important • GR rate is a factor 2.4 higher than the IBL specification of 0.003 Hz

  4. Rates of GR errors in August • RunMode does not reduce SEU errors • August data compatible with June data

  5. Plans for August FE-I4-A irradiation • SEU measurements is Plan on :https://atlpix01.cern.ch/elog/FEI4_SEU_measurements/33 • Christian Gallrapp and his student will start measurements on the same chips the week of 17 August with time shared with SEU • Please make comment to SEU plans

  6. Spare

  7. Classification of GR errors • 1)PRDlike resets: All read GR bits zero SR21~100, SR24~0, SR25~0 • 2)Write glitch inside GR: One bit flip in GR, ErrorFlagb(SR24)=0, WrRegDataErr(SR25)=any • 3)Normal GR SEU: one bit in GR is flipped, SR24>0, SR25=0 • 4)Efuse errors: same type of SEU hard triple memory, but reset and some logic with ARM cells, reload to GR from PROM (actually 0) if single SEU bit flips in triple memory. Difficult for interpretation as refresh mechanism was not working correctly due to the bug in the chip. • 5)”Frozen” bits in several words at the end of sum long runs. Rare and not easy to reproduce. It is not excluded that it is related to IO board irradiation in the beam area.

  8. Base of calculation of GR errors rates • Assume PS beam perfectly aligned on GR. From beam profile from PR in analog scan Flux=51 1010 protons/cm2/spill. For conservative cross-section calculation use safety factor 2 for bad alignment, Flux= 25.5 1010 protons/cm2/spill. • IBL TDR pixel rate at R=33.25 mm, pileup 75 events, L=~3 1034 cm-2sec-1 (with safety factor 1.5 to nominal IBL luminosity) the pixel hit rate is 490 Mhz/cm2 , suppose hit multiplicity 2 hits/track, track Rate= 0.25 109 Hz/cm2 • IBL TDR specification for GR SEU rate is < 1(24 hours) per module. Assuming 448 chips in 224 modules it corresponds to the goal of total SEU rate in 448 IBL chips GRSEU < 0.003 Hz

  9. Absence of Cref=15 structure • According to Malte last data loaded to GR is Cref=15 in the word#34 • To be consistent with absence of correlation with Cref=15 pattern, we should assume that Cref=15 pattern is mostly erased by SEU in ARM cells of Data Register

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