CS-447– Computer Architecture
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CS-447– Computer Architecture M,W 2:30 - 3:50pm Lecture 6 Instruction Set Architecture. Sep 3 rd , 2008 Majd F. Sakr [email protected] www.qatar.cmu.edu/~msakr/15447-f08/. Hypothetical Machine. Consider the following hypothetical machine:

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Sep 3 rd 2008 majd f sakr msakr qatar cmu qatar cmu msakr 15447 f08

CS-447– Computer Architecture M,W 2:30 - 3:50pmLecture 6Instruction Set Architecture

Sep 3rd, 2008

Majd F. Sakr

[email protected]

www.qatar.cmu.edu/~msakr/15447-f08/


Hypothetical machine

Hypothetical Machine

Consider the following hypothetical machine:

# registers = 16 {R0 to R15} require 4-bits to address them (24 = 16)

# memory locations = 256 {M0 to M255} require 8-bits to address them (28 = 256)


Hypothetical machine cont d

Hypothetical Machine (cont’d)

# instructions = 32{Inst0 to Inst31} require 5-bits to be controlled (25 = 32)

where Inst15 = Add (instruction # 15)& Inst9 = Load (instruction # 9)


Example 1 add r0 r4 r11

Example 1: Add R0, R4, R11


The instruction

The instruction

In fact, each piece of an instruction can be considered as an individual number, & placing these numbers side by side forms the instruction.


Example 2 load r13 127

Example 2: Load R13, 127


The instruction1

The instruction

In fact, the instruction format Example: OpCode, Operand, Operand, Operandis fixed only for a specific operation


Sep 3 rd 2008 majd f sakr msakr qatar cmu qatar cmu msakr 15447 f08

Note

  • When the OpCode consist of a memory R/W, the operand, Source Register 1 & 2 are combined to form the address field of the instruction.

  • When the OpCode consist of an immediate instruction, the operand, Source Register 1 & 2 are combined to form the constant whenever that is required.


The instruction2

The Instruction

  • OpCode: basic operation of the instruction

  • Destination Register: register where the result of the operations will be loaded

  • Source Register 1 & 2: registers where the data will be operated on


Instruction size data word size

Instruction size = data word size

As you can see from counting the number of bits, this hypothetical machine instruction takes exactly 17-bits which should be the same size as a data word.


Design by starting with the instruction size

x

x

x

Design by Starting with the Instruction Size

We would like to design a machine with:

  • Instruction size = 8 bits

  • Instruction number = 8

  • No Operation

  • Add

  • Sub

  • Branch

  • Load

  • Store

  • Increment

  • Decrement

3-bits of the instruction word will be reserved to control the 8 desired instructions


Design by starting with the instruction size1

Design by Starting with the Instruction Size

So we are left with 5-bits for the operands, With which we can address at most:

  • 32 (= 25) memory locations

  • 32 (= 25) registers

    But if we chose to do so, we will be restricted in the number of operands in the instructions to one


Design by starting with the instruction size2

x

x

x

Design by Starting with the Instruction Size

On the other hand if we wish to have instructions with 2 explicit operands; that is still possible with the 5-bits left.

How ? ! ?


Sep 3 rd 2008 majd f sakr msakr qatar cmu qatar cmu msakr 15447 f08

x

x

x

How ? ! ?

3

4

5

6

7

Using bits 3 with 4 and bits 5 with 6 to address 4 registers.


Results

Results

  • 8 Instructions

  • 2 operands addressing 4 registers with 2-bits each

  • 1 operand of 5-bits addressing 32 memory locations

    Note:# operands increases # registers decreases


Consider this instruction set

Consider this Instruction Set


Execution of a simple program

Execution of a simple program

The following program was loaded in memory starting from memory location 0.

0000 Load R2, ML4 ; R2 = (ML4) = 5 = 1012

0001 Read R3, Input14 ; R3 = input device 14 = 7

0010 Sub R1, R3, R2 ; R1 = R3 – R2 = 7 – 5 = 2

0011 Store R1, ML5 ; store (R1) = 2 in ML5


The program in memory

The Program in Memory


Load r2 ml4 010 10 0110

LoadR2, ML4 ; 010100110

R1

R3

I.R.

010100110

R2

000000101

...

P.C.

0

1

Load

CPU


Read r3 input14 100 11 0100

ReadR3, Input14; 100110100

010100110

100110100

R1

R3

000000111

R2

...

000000101

1

2

Read

CPU


Sub r1 r3 r2 000 01 1110

SubR1, R3, R2; 000011110

100110101

000011110

R1

R3

000000010

000000111

R2

...

000000101

2

3

000000101

000000111

Sub

CPU


Store r1 ml5 011 01 0111

Store R1, ML5; 011010111

Next Instruction

011010111

R1

R3

Don’t Care

000000010

000000111

R2

...

000000101

3

4

Store

CPU


In the memory

BeforeProgramExecution

AfterProgramExecution

In the Memory

000000010


Instruction formats

Instruction Formats

  • Layout of bits in an instruction

  • Includes OpCode

  • Includes (implicit or explicit) operand(s)

  • Usually more than one instruction format in an instruction set


Instruction length

Instruction Length

  • Affected by and affects:

    • Memory size

    • Memory organization

    • Bus structure

    • CPU complexity

    • CPU speed

  • Trade off between powerful instruction types and saving space (bits).


Allocation of bits

Allocation of Bits

  • Number of addressing modes

  • Number of operands

  • Register versus memory

  • Number of registers

  • Address range

  • Address granularity


Addressing modes

Addressing Modes

  • Immediate

  • Direct

  • Indirect

  • Register

  • Register Indirect

  • Displacement (Indexed)

  • Stack


Immediate addressing

Immediate Addressing

  • Operand is part of instruction

  • The address field points to the operand

  • e.g. ADD 525

    • Add 525 to contents of accumulator

    • 525 is the operand

  • No memory reference to fetch data

  • Fast

  • Limited range


Immediate addressing diagram

Immediate Addressing Diagram

Instruction

OpCode

Operand

Example: ADD 525 ; AC = AC + 525

In an Accumulator-Based machine, we would like to add 525 to the accumulator, the result will be stored in the accumulator itself.


Direct addressing

Direct Addressing

  • Address field contains address of operand

  • Effective address (EA) = address field A

  • e.g. ADD A

    • Look in memory at address A for operand

    • Add contents of (A) to accumulator


Direct addressing cont d

Direct Addressing (cont’d)

  • Single memory reference to access data

  • No additional calculations to work out effective address

  • Limited address space


Direct addressing diagram

Direct Addressing Diagram

Instruction

Memory

OpCode

Operand

Operand

Example: ADD (Addr2) ; AC = AC + (2); (2) = 255


Indirect addressing 1

Indirect Addressing (1)

  • Memory cell pointed to by address field contains the address of (pointer to) the operand

  • EA = (A)

    • Look in A, find address (A) and look there for operand

  • e.g. ADD (A)

    • Add contents of cell pointed to by contents of A to accumulator


Indirect addressing 2

Indirect Addressing (2)

  • Large address space

  • 2n where n = address word length

  • May be nested, multilevel, cascaded

    • e.g. EA = ((A))

      • Draw the diagram yourself

  • Multiple memory accesses to find operand

  • Hence slower


Indirect addressing diagram

Indirect Addressing Diagram

Instruction

Memory

OpCode

Operand

Pointer to Operand

ADD ((1)); AC = AC + ((1))

((1)) = (3) = 255 = operand

Operand

Memory


Register addressing 1

Register Addressing (1)

  • Operand is held in register named in address field

  • EA = R

  • Limited number of registers

  • Very small address field needed

    • Shorter instructions

    • Faster instruction fetch


Register addressing 2

Register Addressing (2)

  • No memory access

  • Very fast execution

  • Very limited address space

  • Multiple registers helps performance

    • Requires good assembly programming or compiler writing

    • C programming:

      • register int a;


Register addressing diagram

Register Addressing Diagram

Registers

Instruction

OpCode

Operand

Operand

ADD R3 ; AC = AC + R3; AC = AC + 255


Register indirect addressing

Register Indirect Addressing

  • Similar to indirect addressing

  • EA = (R)

  • Operand is in memory cell pointed to by contents of register R

  • Large address space (2n)

  • One fewer memory access than indirect addressing


Register indirect addressing diagram

Register Indirect Addressing Diagram

Instruction

Memory

OpCode

Operand

Registers

Operand

Pointer to Operand

Example:ADD (R3) ; AC = AC + (R3) = AC + (1); AC = AC + 255


Displacement addressing

Displacement Addressing

  • EA = A + (R)

  • Address field hold two values

    • A = base value

    • R = register that holds displacement

    • or vice versa


Displacement addressing diagram

Displacement Addressing Diagram

Instruction

Memory

OpCode

Register R

Address A

Operand

Registers

Pointer to Operand

+

ADD (R2, BaseAddress) ; AC = AC + ; (R2+BaseAddress) ; AC = AC + (1) = AC + 255


Relative addressing

Relative Addressing

  • A version of displacement addressing

  • R = Program counter, PC

  • EA = A + (PC)

  • i.e. get operand from A cells from current location pointed to by PC


Base register addressing

Base-Register Addressing

  • A holds displacement

  • R holds pointer to base address

  • R may be explicit or implicit


Indexed addressing

Indexed Addressing

  • A = base

  • R = displacement

  • EA = A + R

  • Good for accessing arrays

    • EA = A + R

    • R++


Combinations

Combinations

  • Postindex

  • EA = (A) + (R)

  • Preindex

  • EA = (A+(R))

  • (Draw the diagrams)


Stack addressing

Stack Addressing

  • Operand is (implicitly) on top of stack

  • e.g.

    • ADDPop top two items from stackand add


Byte ordering big endian

0

Byte 4

Byte 0

Byte 5

1

Byte 1

Byte 6

Byte 2

2

Byte 7

3

Byte 3

Byte ordering – Big Endian

Bytes are ordered left to right (starting at “big end”)

Byte 0 at the leftmost (most significant) to byte 3 at the rightmost (least significant)

Word 0

Word 1

Bit 0

Bit 31


Byte ordering little endian

3

Byte 7

Byte 3

2

Byte 6

Byte 2

Byte 5

Byte 1

1

Byte 4

0

Byte 0

Byte ordering – Little Endian

  • Byte 3 at the leftmost (MSB) to byte 0 at the rightmost (LSB)

  • Bytes are ordered right to left (starting at “little end”)

Word 0

Word 1

Bit 0

Bit 31


An example isa ia32

An Example ISA – IA32


Moving data ia32

%eax

%edx

%ecx

%ebx

%esi

%edi

%esp

%ebp

Moving Data: IA32

  • Moving Data

    movlSource,Dest:

    • Move 4-byte (“long”) word

    • Lots of these in typical code

  • Operand Types

    • Immediate: Constant integer data

      • Like C constant, but prefixed with ‘$’

      • E.g., $0x400, $-533

      • Encoded with 1, 2, or 4 bytes

    • Register: One of 8 integer registers

      • But %esp and %ebp reserved for special use

      • Others have special uses for particular instructions

    • Memory: 4 consecutive bytes of memory

      • Various “address modes”


Movl operand combinations

movl $0x4,%eax

temp = 0x4;

movl $-147,(%eax)

*p = -147;

movl %eax,%edx

temp2 = temp1;

movl %eax,(%edx)

*p = temp;

movl (%eax),%edx

temp = *p;

movl Operand Combinations

  • Cannot do memory-memory transfer with a single instruction

Source

Dest

Src,Dest

C Analog

Reg

Imm

Mem

Reg

movl

Reg

Mem

Mem

Reg


Simple addressing modes

Simple Addressing Modes

  • Normal(R)Mem[Reg[R]]

    • Register R specifies memory addressmovl (%ecx),%eax

  • DisplacementD(R)Mem[Reg[R]+D]

    • Register R specifies start of memory region

    • Constant displacement D specifies offsetmovl 8(%ebp),%edx


Indexed addressing modes

Indexed Addressing Modes

  • Most General Form

  • D(Rb,Ri,S)Mem[Reg[Rb]+S*Reg[Ri]+ D]

    • D: Constant “displacement” 1, 2, or 4 bytes

    • Rb: Base register: Any of 8 integer registers

    • Ri:Index register: Any, except for %esp

      • Unlikely you’d use %ebp, either

    • S: Scale: 1, 2, 4, or 8

  • Special Cases

  • (Rb,Ri)Mem[Reg[Rb]+Reg[Ri]]

  • D(Rb,Ri)Mem[Reg[Rb]+Reg[Ri]+D]

  • (Rb,Ri,S)Mem[Reg[Rb]+S*Reg[Ri]]


Address computation examples

Address Computation Examples

%edx

0xf000

%ecx

0x100


Some arithmetic operations

Some Arithmetic Operations

FormatComputation

  • Two Operand Instructions

    addl Src,DestDest = Dest + Src

    subl Src,DestDest = Dest - Src

    imullSrc,DestDest = Dest * Src

    sall Src,DestDest = Dest << SrcAlso called shll

    sarl Src,DestDest = Dest >> SrcArithmetic

    shrl Src,DestDest = Dest >> SrcLogical

    xorl Src,DestDest = Dest ^ Src

    andl Src,DestDest = Dest & Src

    orl Src,DestDest = Dest | Src


Some arithmetic operations1

Some Arithmetic Operations

FormatComputation

  • One Operand Instructions

    inclDestDest = Dest + 1

    declDestDest = Dest - 1

    neglDestDest = - Dest

    notlDestDest = ~ Dest


Another example isa y86

OF

ZF

SF

Another Example ISA, Y86

Program registers

Condition codes

  • Program Registers

    • Same 8 as with IA32. Each 32 bits

  • Condition Codes

    • Single-bit flags set by arithmetic or logical instructions

      • OF: OverflowZF: ZeroSF:Negative

  • Program Counter

    • Indicates address of instruction

  • Memory

    • Byte-addressable storage array

    • Words stored in little-endian byte order

Memory

%eax

%esi

%ecx

%edi

PC

%edx

%esp

%ebx

%ebp


Y86 instructions

Y86 Instructions

  • Format

    • 1--6 bytes of information read from memory

      • Can determine instruction length from first byte

      • Not as many instruction types, and simpler encoding than with IA32

    • Each accesses and modifies some part(s) of the program state


Encoding registers

%eax

0

%esi

6

%ecx

1

%edi

7

%edx

2

%esp

4

%ebx

3

%ebp

5

Encoding Registers

  • Each register has 4-bit ID

    • Same encoding as in IA32

  • Register ID 8 indicates “no register”

    • Will use this in our hardware design in multiple places


Instruction example

Generic Form

Encoded Representation

addl rA, rB

6

0

rA

rB

Instruction Example

  • Addition Instruction

    • Add value in register rA to that in register rB

      • Store result in register rB

      • Note that Y86 only allows addition to be applied to register data

    • Set condition codes based on result

    • e.g., addl %eax,%esiEncoding: 60 06

    • Two-byte encoding

      • First indicates instruction type

      • Second gives source and destination registers


Arithmetic and logical operations

Instruction Code

Function Code

addl rA, rB

xorl rA, rB

andl rA, rB

subl rA, rB

6

6

6

6

2

3

1

0

rA

rA

rA

rA

rB

rB

rB

rB

Arithmetic and Logical Operations

  • Refer to generically as “OPl”

  • Encodings differ only by “function code”

    • Low-order 4 bytes in first instruction word

  • Set condition codes as side effect

Add

Subtract (rA from rB)

And

Exclusive-Or


Move operations

rA

8

rA

rB

rB

rB

rrmovl rA, rB

4

3

2

5

0

0

0

0

rA

rB

irmovl V, rB

mrmovl D(rB), rA

rmmovl rA, D(rB)

V

D

D

Move Operations

  • Like the IA32 movl instruction

  • Simpler format for memory addresses

  • Give different names to keep them distinct

Register --> Register

Immediate --> Register

Register --> Memory

Memory --> Register


Jump instructions

Jump When Equal

Jump When Not Equal

Jump Unconditionally

Jump When Greater

Jump When Greater or Equal

Jump When Less or Equal

Jump When Less

jge Dest

jl Dest

je Dest

jmp Dest

jg Dest

jne Dest

jle Dest

Dest

Dest

Dest

Dest

Dest

Dest

Dest

7

7

7

7

7

7

7

0

4

3

2

1

5

6

Jump Instructions

  • Refer to generically as “jXX”

  • Encodings differ only by “function code”

  • Based on values of condition codes

  • Same as IA32 counterparts

  • Encode full destination address

    • Unlike PC-relative addressing seen in IA32


Stack operations

pushl rA

popl rA

a

rA

b

rA

0

8

0

8

Stack Operations

  • Decrement %esp by 4

  • Store word from rA to memory at %esp

  • Like IA32

  • Read word from memory at %esp

  • Save in rA

  • Increment %esp by 4

  • Like IA32


Subroutine call and return

call Dest

Dest

ret

8

9

0

0

Subroutine Call and Return

  • Push address of next instruction onto stack

  • Start executing instructions at Dest

  • Like IA32

  • Pop value from stack

  • Use as address for next instruction

  • Like IA32


Miscellaneous instructions

nop

halt

0

1

0

0

Miscellaneous Instructions

  • Don’t do anything

  • Stop executing instructions

  • IA32 has comparable instruction, but can’t execute it in user mode

  • We will use it to stop the simulator


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