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CAD contest. iLab128G Yung-Chun Hu & Chian -Wei Liu & Chen-Yu Lin & A- Rei 2013/09/02. Outline. Introduction Boolean Logic Adder Flow Experimental Results Future work. Introduction. Given: A circuit & Macro Blocks Derive: A new circuit with minimized cost

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#### Presentation Transcript

iLab128G

Yung-Chun Hu & Chian-Wei Liu & Chen-Yu Lin & A-Rei

2013/09/02

### Outline

• Introduction

• Boolean Logic

• Flow

• Experimental Results

• Future work

### Introduction

Given:

A circuit & Macro Blocks

Derive:

A new circuit with minimized cost

(Macro blocks are 0 cost)

### Introduction

• assign out = &in

• assign out = |in

• assign out = ^in

• assign out = ~&in

• assign out = ~|in

• assign out = ~^in

• assign out = in2[in1]

• assign out = in1 + in2

• assign out = in1 + in2 + in3

• assign out = in1 + in2 + in3 + in4

• assign out = in1 * in2

• assign out = (in1 + in2) * in3

• assign out = in1 * in2 + in3 * in4

• assign out = in1 * in2 + in3 * in4 + in5 * in6

Boolean Logic

MUX

Arithmetical Logic

### Boolean Logic

• Step1: Finding continuous AND/XOR

• Step2: Appending external inverter

• Step3: Map

• Step4: Exhaustively choose roots from candidates.

### Boolean Logic

If we have two AND macro blocks…

A

B

D

C

7

10

11

14

If we greedily choose the max node-reduction roots, the result is C and D.

However, the optimal solution is A and B.

• Cut

• 3-cut-based

• Connect

• Connect FA/HA

• Invert FA/HA function (really connect)

### Flow

Parser (including design & library)

Library type

Hybrid

Index (MUX)

Boolean Logic

Step1: Cut & Match

Step1: Structure

Step1: Finding AND/XOR

Step2: Selection

Step2: Map

Step2: Map

Step2: Map

Step3: Map

Optimization

Resyn2

Gen_lib selection

??

Output & Verification

### Future work

• Integration

• Multiplier (shift)