International Technology Roadmap for Semiconductors 2006 ITRS Update/ORTC Product Models Status

1. International Technology Roadmap for Semiconductors 2006 ITRS Update/ORTC Product Models Status [Including 1Q06 SIA/SICAS* Industry Technology Capacity Demand Analysis] For Public 07/12/06 Conference SEMICON / San Francisco, CA (Draft Rev 0, 06/30/06) * Semiconductor Industry Association / Semiconductor Industry Capacity Statistics 2006 ITRS Update Work in Progress – Do Not Publish

2. Traditional ORTC Models 2005 ITRS Executive Summary Fig 5 Source: 2005 ITRS Document online at: http://www.itrs.net/Links/2005ITRS/Home2005.htm 2006 ITRS Update Work in Progress – Do Not Publish

3. ORTC Overview – 2006 Update ITRS - Unchanged • One standard TWG table technology trend header • Presently continue to use DRAM stagger-contacted M1 as typical industry lithography driver • Transitioned to product-oriented technology trend drivers and cycles* • ORTC Table 1a,b - MPU/ASIC M1 Half-Pitch Trend • Stagger-contacted, same as DRAM • 2.5-year Technology Cycle* (.5x/5yrs) • 180nm/2000; 90nm/2005; 45nm/2010(equal DRAM) • Then continue on a 3-year Technology Cycle*, equal to DRAM 2010-2020 • ORTC Table 1a,b - STRJ Flash Poly (Un-contacted dense lines) • 2-year Technology Cycle* (0.5x/4yrs) • 180nm/2000; 130nm/2002; 90nm/2004; 65nm/2006 • Then 3-year Technology Cycle* 1 year ahead of DRAM ’06-’20 • ORTC Table 1a,b – MPU/ASIC Printed Gate Length per FEP and Litho TWG ratio relationship to Final Physical Gate Length - UNCHANGED from the 2005 ITRS targets (3-year cycle* after 2005) • TWG table Product-specific technology trend driver header items are added to individual TWG tables from ORTC Table 1a&b • Chip Size Models are connected to proposals and historical trends, incl. new Flash Model • Function Size [Logic Gate; SRAM Cell; Dram Cell; Flash Cell (SLC, MLC)] • Functions/Chip [Flash; DRAM; High Performance (hp) MPU; Cost Perf. (cp) MPU] • Chip Size [hp MPU; cp MPU; DRAM; Flash] *Note: Cycle = time to 0.5x linear scaling every two cycle periods ~ 0.71x/ cycle 2006 ITRS Update Work in Progress – Do Not Publish

4. 2005 Definition of the Half Pitch [No single-product “node” designation; DRAM half-pitch still litho driver; however, other product technology trends may be drivers on individual TWG tables] FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/2 DRAM ½ Pitch = DRAM Metal Pitch/2 MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2 • Poly • Pitch • Metal • Pitch 8-16 Lines Typical flash Un-contacted Poly Typical DRAM/MPU/ASIC Metal Bit Line 2006 ITRS Update Work in Progress – Do Not Publish

5. Fig 3 Production Ramp-up Model and Technology Cycle Timing 100M 200K Development Production 10M 20K 1M 2K Alpha Tool Beta Tool Production Tool Volume (Parts/Month) 100K Volume (Wafers/Month) 200 First Two Companies Reaching Production 10K 20 First Conf. Papers 1K 2 0 12 24 -24 -12 Months Source: 2005 ITRS - Exec. Summary Fig 3 2006 ITRS Update Work in Progress – Do Not Publish

6. 2005 (’05-’20) ITRS Technology Trends DRAM M1 Half-Pitch : 3-year cycle 2007 2001 2001 2003 2003 2005 2005 2006 2008 2009 2012 2015 2018 2020 14 2000 [Actual] 2000 [Actual] 2002 [Actual] 2002 [Actual] 2004 2004 2010 2013 2016 2019 65 90 90 45 32 22 16 130 130 180 180 151 107 80 71 57 50 2-Year Technology Cycle [‘98-’04] Year of Production Year of Production Year of Production 2005 ITRS Flash Poly Half-Pitch Technology: 2.0-year cycle until 1yr ahead of DRAM @65nm/’06 3-Year Technology Cycle 3-Year Technology Cycle 2008 2010 2013 2016 2019 2020 2006 2009 2012 2015 2018 Technology - Uncontacted Poly H-P (nm) Technology - Contacted M1 H-P (nm) Technology - Contacted M1 H-P (nm) 13 2001 2002 2003 2004 2006 2007 2008 2009 2012 2015 2018 2020 65 45 32 22 16 57 151 107 76 50 2010 2013 2016 2019 45 32 22 16 180 [130] 90 [ 65] 157 136 119 103 78 68 59 52 3-2-Yr Cycle] 2-Year Technology Cycle [’98-’06 ] 2.5-Year Technology Cycle 3-Year Technology Cycle 2005 ITRS MPU M1 Half-Pitch Technology: 2.5-year cycle; then equal DRAM @45nm/2010 2000 [July’02] 2005 [July’08] 14 6 2006 ITRS Update Work in Progress – Do Not Publish

7. Figure 8 ITRS Product Technology Trends Fig 7&8 Simplified – Option 1 After 1998 .71X/2YR MPU M1 .71X/2.5YR Before 1998 .71X/3YR MPU & DRAM M1 & Flash Poly .71X/3YR Flash Poly .71X/2YR Gate Length .71X/3YR GLpr IS = 1.6818 x GLph Nanotechnology (<100nm) Era Begins -1999 2005 - 2020 ITRS Range 2006 ITRS Update Work in Progress – Do Not Publish

8. Fig 4 Technology Cycle Timing Compared to Actual Wafer Production TechnologyCapacity Distribution ITRS Technolgy Cycle 10 W.P.C.= Total Worldwide Wafer Production Capacity(Relative Value *) Source: SICAS** W.P.C W.P.C W.P.C W.P.C W.P.C W.P.C W.P.C W.P.C W.P.C >0.7mm 720nm SIA/SICAS Data**: 1-yr delay from ITRS Cycle Timing to 25% of MOS IC Capacity 0.7-0.4mm 510nm 1 Feature Size (Half Pitch) (mm) 0.4-0.3mm 360nm (Feature Size of Reported Technology Capacity of SICAS Participants) <0.4mm <0.4mm <0.3mm <0.3mm 0.3- 0.2mm <0.2mm <0.2mm 255nm <0.16mm <0.16mm 0.1 <0.12mm 0.2- 0.16mm 180nm = 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual = 2005 ITRS DRAM Contacted M1 Half-Pitch Target 0.16-.12mm 127nm 3-Year Cycle 2-Year Cycle 3-Year Cycle 0.01 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 <0.12mm 90nm Source: 2005 ITRS - Exec. Summary Fig 4 Year * Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for 2005.  The area of each of the production capacity bars corresponds to the relative share of the Total MOS IC production start silicon area for that range of the feature size (y-axis). Data is based upon capacity if fully utilized. ** Source: The data for the graphical analysis were supplied by the Semiconductor Industry Association (SIA) from their Semiconductor Industry Capacity Statistics (SICAS). The SICAS data is collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published by the Semiconductor Industry Association (SIA), as of July, 2005. The detailed data are available to the public online at the SIA website, http://www.sia-online.org/pre_stat.cfm . 2006 ITRS Update Work in Progress – Do Not Publish

9. SICAS 90nm Capacity Tracking Kickoff – 1Q06 Update 0.71x 0.85 to 0.72u to.60u 0.60 to 0.51u to.42u 0.42 to 0.36u to.30u 0.30 to 0.25u to.21u n-2 0.21 to 0.18u to.15u n-1 0.15 to 0.13u to.11u n 0.11 to 0.090u to 0.075u Next TBD?: 20% 1Q07? (2yr Cycle) 1Q08? 3yr Cycle <0.075 to 0.065u to.053u ~28% of Total MOS n+1 [available ca 2Q07?] 2-yrs to >20% of Total MOS for 0.71x Technology Reduction Cycle Source: SIA/SICAS Report: www.sia-online.org/pre_statistics.cfm 2006 ITRS Update Work in Progress – Do Not Publish

10. SICAS 300m Capacity Tracking – 1Q06 Update 2004 – Happy 10th Anniv. SICAS! 10.3% CAGR 11.6% CAGR 11 years intro-intro Wafer Generation 1Q06: 300mm = 22% of Total MOS 200mm = 62% of Total MOS <200mm = 16% of Total MOS 200mm/1Q97 SICAS Tracking Begins (7yrs after Intro) 300mm/1Q04 (3yrs after Intro) Source: SIA/SICAS Report: www.sia-online.org 2006 ITRS Update Work in Progress – Do Not Publish

11. Figure 9 ITRS Product Function Size Fig xx Simplified Logic Gate: NO Design Area Factor Improvement (Only Scaling) SRAM: Gradual Design Area Factor Improvement DRAM: 5f2 Last Design Area Factor Improvement (@ 2 MLC bits/physical cell area) Flash: 4f2 Last Design Physical Area Factor Improvement Flash: (MLC @ 2 bits/cell = 2f2 Equivalent Area Factor) Note for Flash: SLC = Single-Level-Cell Size MLC = Multi-Level-Cell (Electrical Equivalent) Cell Size 2005 - 2020 ITRS Range 2006 ITRS Update Work in Progress – Do Not Publish

12. Chip Size Trends – 2005 ITRS Functions/Chip Model (@Volume Production, Affordable Chip Size**) ** Affordable Production Chip Size Targets: DRAM, Flash < 145mm2 hp MPU < 310mm2 cp MPU < 140mm2 Average Industry 1970-2020 “Moore’s Law” 2x Functions/chip Per 2 years MPU ahead or = “Moore’s Law” 2x Xstors/chip Per 2 years Thru 2010 ** Example Chip Size Targets: 1.1Gt P07h MPU @ intro in 2004/620mm2 @ prod in 2007/310mm2 ** Example Chip Size Targets: 0.39Gt P07c MPU @ intro in 2004/280mm2 @ prod in 2007/140mm2 2005 - 2020 ITRS Range Past  Future 2006 ITRS Update Work in Progress – Do Not Publish

13. Figure 10 ITRS Product Functions per Chip Average Industry 1970-2020 “Moore’s Law” 2x Functions/chip Per 2 years 2005 - 2020 ITRS Range 2006 ITRS Update Work in Progress – Do Not Publish

14. Chip Size Trends – 2005 ITRS DRAM Model 2005: Past  Future 2005 - 2020 ITRS Range 2006 ITRS Update Work in Progress – Do Not Publish

15. Chip Size Trends – 2005 ITRS Flash Model 2005: 2005 - 2020 ITRS Range Past  Future 2006 ITRS Update Work in Progress – Do Not Publish

16. Chip Size Trends – 2005 ITRS MPU Model Max Litho Field 2005 ITRS 834mm2 (26x32) (4x): p16h p19h p22h p10h p13h 800 26% / 2yrs 2.2Bt 4.4Bt Chip Size hp MPU = 82% SRAM Transistors, 18% Core Logic Transistors Growth 417m2 (26x16) 700 cp MPU = 58% SRAM Transistors, 42% Core Logic Transistors 2 Chips per Max Litho Field p07h p02h p04h SRAM Cell Efficiency= 60% Logic Gate Efficiency = 50% 600 1.1Bt 276Mt 552Mt MPU hp Production Chip Size 2005 ITRS (4x): MPU cp Production Chip Size 500 MPU hp Introduction Chip Size MPU cp Introduction Chip Size 400 p16c p19c p22c p10c p13c 3.1 768Mt 1.5Bt (mm2) p10h p07h p04h p98h p00h p02h 2.2Bt Affordable hp MPU 1.1Bt 552Mt 69Mt 138Mt 276Mt 300 310mm2 prod Target: 8G p07c p00c p02c p04c 384Mt 48Mt 96Mt 192Mt 200 p07c p10c p13c p00c p02c p04c Affordable cp MPU 384Mt 768Mt 1.5Bt 48Mt 96Mt 96Mt 140mm2 prod Target: 100 DRAM 0 HP 1995 1998 2001 2004 2007 2010 2013 2016 2019 2022 2025 WAS/IS: 64 45 32 16 90 22 11 8 180 128 360 255 8 MPU: 90 68 45 32 22 16 11 180 136 360 255 [2.5yr Technology Cycle Year of Introduction and Production 2000-2010] 2005 - 2020 ITRS Range Past  Future 2006 ITRS Update Work in Progress – Do Not Publish

17. Summary • DRAM Model stagger-contacted M1 is unchanged from 2005 ITRS (3-year cycle* after 2004) • MPU M1 stagger-contact half-pitch is on a 2.5-year cycle* through 2010/45nm, then 3-year cycle* • Flash Model un-contacted poly half-pitch continues on 2-year cycle* to 1 year ahead of DRAM (contacted) in 2006, then 3-year cycle* • Printed MPU/ASIC Gate Length set by FEP and Litho TWGs ratio agreement, but Physical GL targets remain unchanged and on 3-year cycle* beginning 2005 • Industry Technology Capacity Demand (SICAS) still on 2-year cycle • Total MOS Capacity is growing ~11% CAGR (SICAS), and 300mm Capacity Demand has ramped to 22% of Total MOS • Historical chip size models “connected” to Product scaling rate models, and include design factors, function size, and array efficiency targets • Average industry product “Moore’s Law” met or exceeded throughout 2005-2020 ITRS timeframe [* ITRS Cycle definition = time to .5x linear scaling every two cycle periods] 2006 ITRS Update Work in Progress – Do Not Publish

18. Note: ITRS Table Colorization Code Reference: Backup Source: 2005 ITRS Document online at: http://www.itrs.net/Links/2005ITRS/Home2005.htm 2006 ITRS Update Work in Progress – Do Not Publish

19. ORTC Table 1a,b (Near, Long Term): 2006 ITRS Update Work in Progress – Do Not Publish

20. Label Correction – Should be “bits” ORTC DRAM & Flash Prod Table 1c (Near Term): 2006 ITRS Update Work in Progress – Do Not Publish

21. Label Correction – Should be “bits” ORTC DRAM & Flash Prod Table 1d (Long Term): 2006 ITRS Update Work in Progress – Do Not Publish

22. ORTC Table DRAM Intro 1e,f (Near, Long Term): 2006 ITRS Update Work in Progress – Do Not Publish

23. ORTC MPU cp Table 1g (Near Term): 2006 ITRS Update Work in Progress – Do Not Publish

24. ORTC MPU cp Table 1h (Long Term): 2006 ITRS Update Work in Progress – Do Not Publish

25. ORTC MPU/ASIC hp Table 1i (Near Term): 2006 ITRS Update Work in Progress – Do Not Publish

26. ORTC MPU/ASIC hp Table 1j (Long Term): 2006 ITRS Update Work in Progress – Do Not Publish