Shaodi Wang 004033643

1. EE201C : Stochastic Modeling of FinFET LERand Circuits Optimization based on Stochastic Modeling Shaodi Wang 004033643

2. Outline • Stochastic modeling of FinFET LER • Stochastic modeling based circuits optimization • 22nm FinFET circuits optimization • Conclusion

3. Devices Variability • Line Edge Roughness (LER) • LER is the main variability in FinFET • Gate Dielectric Thickness (Tox) • Random Dopant Fluctuations (RDF) • Metal-gate Work Function (WFV)

4. Line Edge Roughness • Stochastic • Consequence of Lithography processing

5. LER vs. LWR • Line width roughness (LWR)

6. Correlation • Resist-defined • Spacer-defined

7. Correlation

8. Gate LER and Fin LER

9. Gate LER Affection • Fin LWR affects device performance by changing the average Fin width in the channel region. • Gate LWR induce the FG and BG mismatch and offset.

10. Stochastic modeling of Gate LWR

11. Stochastic modeling of Gate LWR Spacer Forming Gate: Resist Forming Gate:

12. Experimental grids are established

13. Result

14. Results

15. Results

16. Results

17. Outline • Stochastic modeling of FinFET LER • Stochastic modeling based circuits optimization • 22nm FinFET circuits optimization • Conclusion

18. Stochastic Circuits Optimization • Performance vs. scaling • Power vs. scaling • Leakage Power • Dynamic Power

19. Optimization methodology • Stochastic timing analysis • Instead of static timing analysis • Every path can be critical path • Every path has a probity to become a critical path • The given yield to constrain the clock frequency

20. Optimization process

21. Models: • Power Model

22. Models • Delay model

23. Models • Devices model depends on different devices. • MOSFET • SOI • FinFET • Devices simulation results • Output from Spice, etc. • Empirical fitting model

24. Tolerance modeling • Process variation • LER • RDF (Not important for FinFET) • Intra-die, inter-die and across-die variation • Supply voltage variation • Vdd and Ground noise

25. Tolerance modeling • Variation affection • Example: Vt shift and follows a Gaussian distribution • Delay distribution: • One stage delay: • N stage path delay: • Average Off Current: • Assume Ioff follows Gaussian distribution

26. Tolerance modeling • Given a clock period tCK • Each path has a delay distribution. Delay over tCK results failure. • The total yield: • Given the yield and reverse the equation to solve tCK.

27. Thermal modeling • Temperature dependence • Subthreshold leakage • Mobility model • Wire resistance model • Heat-sink model

28. Results

29. Results

30. Defects • This works contribute the process variation into the Vt variability. However, the device performance variability cannot be easily appropriately modeled by Vt.

31. Outline • Stochastic modeling of FinFET LER • Stochastic modeling based circuits optimization • 22nm FinFET circuits optimization • Conclusion

32. FinFET variability • The FinFET is 22nm technology. • The thin channel suppresses short channel effects. • Low doping makes RDF affection lower. • The restriction of Tox is released. • LER become the important process variation. • Voltage supply noise is still a problem

33. FinFET optimization based on Stochastic modeling FinFET Device LER Simulation Principle component analysis on FinFET LER results Fitting model to FinFET behavior Transfer the principle component from device LER to model parameters Circuits performance variability is done based on model

34. FinFET optimization based on Stochastic modeling • FinFET 3-D LER MC simulation is done based on sentaurus TCAD tool. • Non-variation current behavior is obtained. ( Works in model fitting) • Key parameters are obtained • Threshold voltage • Saturation voltage • Ion current • DIBL

35. FinFET optimization based on Stochastic modeling • Principle component analysis performed on device LER results • Calculate the covariance matrix of the results of FinFET. • Covariance matrix: • Calculate the eigen vectors and eigen values • Eigen vectors Eigen value • These eigen vectors are independent

36. FinFET optimization based on Stochastic modeling • Calculate the sensitive vectors of devices key behavior parameters to model parameters. • My model has 9 parameters. This sensitive vectors are the 4 devices key parameters’ derivation to 9 parameters of model • Calculate the principle components in emperical model

37. FinFET optimization based on Stochastic modeling • Variability model in my work • LER Variation • Based on PCA, I used 9 parameters in the model to represent the LER variability. ( Ion, Ioff, Vt, CLM, Vtsat, Vt,lin …) • Voltage supply variation • I model this into the supply voltage Vdd variability. • Across-die, inter-die and intra-die variation • I model this by threshold voltage variability • All of these 3 variation are independent • Model delay variability • Based on MC simulation.

38. FinFET optimization based on Stochastic modeling • Optimization process • Given the restriction ( Power and Yield) • Outer loop : optimized parameters ( Vt, W and etc) • Inner loop : optimized parameters (Vdd) • In each one of the all loop: • 100 samples MC performed to get the distribution of one stage Delay. • Based on the given Yield, using iteration to find the chip clock frequency. • Calculate the total power, the power must < Power restriction. • Choose the fast clock in given Power restriction.

39. FinFET optimization based on Stochastic modeling • Optimization Results • Optimized Block : Gate 5000, longest path 22 stages.

40. Conclusion • LER is one of the important variability in FinFET technology. • As power restricts devices scaling, circuits optimization becomes an important process to reduce power. • FinFET circuits optimization is done by considering LER, supply voltage, process variation.

41. Reference • Kedar Patel, et all, “L. I. Smith. “A Tutorial on Principal Components Analysis”. Cornell University, USA, 2002. ”, IEEE Transactions on Electronics Devices, vol. 56, no. 12, Dec. 2009. • L. I. Smith. “A Tutorial on Principal Components Analysis”. Cornell University, USA, 2002. • D. J. Frank, et all, “Optimizing CMOS technology for maximum performance” , IBM J. RES & DEV. vol.50, no. 4/5, 2006