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MAVEN PFFSW STATUS 2/07/2012

MAVEN PFFSW STATUS 2/07/2012. Operational Status. Interface Documents, Meetings STATIC 1/6/12 kickoff. Data processing description not available. Waiting for McFadden.

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MAVEN PFFSW STATUS 2/07/2012

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  1. MAVEN PFFSW • STATUS • 2/07/2012

  2. Operational Status Interface Documents, Meetings • STATIC 1/6/12 kickoff. Data processing description not available. Waiting for McFadden. • HV & RTS meeting. Good agreement on operations in general. Many changes required. Focused upon the Inst Start, HV ON and HV OFF interactions Development • Completed MAG Processing & Delta-Mod (Redone from original requirements) • Completed PWR Actuator logic (2-bit / actuator, requests) • Detailed RTS HV ON (in general) for SWIA, SWEA, STATIC • Completed RTS HV ON & START for SWIA • Completed SWIA HV RAMP • Completed SWIA LUT loading (~1000 wds/sec) -> 8 seconds to load 1 LUT • Wrote SWEA & STATIC HV RAMP • Wrote SWEA LUT loading IV&V • Received Level 5 Requirements Validation Report Next Month • Need to get description of STATIC processing (13 APIDs) • Need to get agreement on RTS 0-5 , (Cold and Warm Resets, Safe, Normal, Eng modes) • Need to get FSW limit monitors and actions specified

  3. HFS Status Interface Documents, Meetings • 1/10/12 Kickoff meeting on HFS requirements. • 1/31/12 UCB-LM HFS telecon • 2/01/12 UCB-LM HFS telecon Development • FSW V2.0 Selected to minimize impact on FSW development, running experience • Needed time to test the HFS • Developed HFS documentation to support delivery to LM • Replaced RTS database for additional functionality over V2.0 • Updated support utilities to correctly generate RTS EEPROM patch Issues • LM whining about the changing CTM • Over 100 changes have been made in 2011 • CTM is not under any sort of version control, not in any ICD • This has severely impacted FSW development in January Plan • We will send a preview CTM a “month before next delivery”

  4. HV and RTS • LUT Loads: • - FSW will process LUT loads on separate interrupt from science • - Should be able to do LUT loads, HV ramps and Science at same time • - Appx 128 CDI's per interrupt • - At 8 Hz rate, LUTs are loaded at 1024 Words/sec • - Will have a known and consistent loading time • POWER ON or RESET • Driver will run the INST_START script when inst turned on. • If the Instrument wants a “soft reset” then it should be in the START script.

  5. HV and RTS RTS "INST_START" (used by FSW at turn on) - should have a FPGA Reset (turns HV off) - Enable Housekeeping packets right away - Enables the HV supplies - Disable LUT checksums while loading LUTs - Zero unused FPGA memory before loading LUTs - Command FSW to load first SLUT, MLUT (STATIC) - Start_RTS(INSTHVON) to ramp RAW, MCP and ACC - Enable sweeping - Enable Science messages - Command FSW to load any other SLUT and MLUT

  6. HV and RTS RTS "INSTHVON" (called by INST_START and Fault Protection) - Sends a SIFCTRL (21xxx1) to enable HV - Sends the HVENABLE KEYS (in flight mode) - Command FSW to Ramp RAW - Command FSW to Ramp MCP - Command FSW to Ramp ACC RTS "INSTHVOFF" (called by Fault Protection) - Sends a SIFCTRL (21xxx0) to disable HV FAULT LOGIC - Make sure instrument analog housekeeping is used to indicate instrument is alive. - On LUT checksum fault, reloading LUTs must include zero fill areas.

  7. INST Manager Generic Instrument Manager Design (type1)

  8. INST Manager Generic Instrument Manager Design (type 2)

  9. INST Manager Rev’d Generic Instrument Manager Design (type1 revised)

  10. INST Manager Rev’d Generic Instrument Manager Design (type 2 revised)

  11. HV & RTS etc

  12. EEPROM

  13. Test Environment GSEOS Status: • Instrument simulation (partially done) • Limit checking error messages (uses raw values, not converted) GSEOS Python Test Scripts, Displays • Need to Build Operational Test Scripts FSW Development Platform: • Need to Configure with Attenuator simulation for Operational Testing • Need to Configure with Instrument simulation for Operational Testing Testing Personnel: • No changes

  14. SPRs and SCRs

  15. Charts CHARTS

  16. Op SLOC

  17. Module Status Chart

  18. Metrics Chart

  19. Margin Chart Finished adding LUTs to EEPROM. None in Flash Calculations performed in Analyses.xls

  20. Defect Chart

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