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Bus Interfacing

Bus Interfacing. Processor-Memory Bus High speed memory bus Backplane Bus Processor-Interface bus This is what we usually mean by “the bus” ISA/PCI/VME I/O Bus Standard Interfaces SCSI, ATAPI. Processor-Memory Bus. This bus connects the CPU to RAM Designed for maximal bandwidth

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Bus Interfacing

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  1. Bus Interfacing • Processor-Memory Bus • High speed memory bus • Backplane Bus • Processor-Interface bus • This is what we usually mean by “the bus” • ISA/PCI/VME • I/O Bus • Standard Interfaces • SCSI, ATAPI

  2. Processor-Memory Bus • This bus connects the CPU to RAM • Designed for maximal bandwidth • Usually wide, 32 bits or more • To further increase bandwidth we use a Cache • Burst access between cache and memory, early restart Cache Miss STALL, Start Burst read from RAM PA[3:2] 1 Release Pipe STALL Continue Burst read from RAM PA[3:2] 4 2 3

  3. RAM Technology • Static RAM used for Cache • Fast 5-40ns (but expensive) • Predictable response time (constant) • Cache line n*32 bits • Burst read can be made fast • Exploit locality • Dynamic RAM used for primary memory • Needs “refresh”, (not constant access time) • Bandwidth, (throughput) • Bus width / Access time

  4. Memory Bus 4*32 Each access transfers 128 bits 00xx 01xx 10xx 11xx 32 Each RAM bank is only accessed every fourth cycle on “burst read” 00xx 01xx 10xx 11xx

  5. On Chip Cache (1st level) CP0 • Using separate Instruction and Data • caches, we can read a Hit simultaneously • for both Instruction and Data • In this model 1st level caches use virtual • address, and must pass TLB on Cache miss • 1st level cache must be fast • Limited area on chip • Usually 8-64 kb IM DE EX DM Instr Cache Data Cache

  6. Backplane Bus Virtual Address Bus Adapter Primary Memory RAM CP0 Control 2nd level Cache IM DE EX DM Physical Addr 1st level Cache Data TLB HD Interface Serial Interface Graphics Adapter Sound Card

  7. Synchronous Bus • A single clock controls the protocol • Pros • Simple (one FSM) • Fast • Cons • Clock skew limits bus length • All devices work on the same speed (clock) • Suitable for Processor-Memory Bus

  8. Asynchronous • Uses a handshaking to implement a transaction protocol • Pros • Versatile, generic protocols • Dynamic data rate • Cons • More complex, two communication FSMs • Slower, (but usually can be made quite fast)

  9. Asynchronous Protocol • ReadReq • DataReady • Ack Master Slave ReadReq Ack Wait for Data DataReady Ack

  10. Increase Bus Bandwidth • Timing & Protocol • Faster timing, less protocol activity, (but less versatile) • Data bus width • More bus lines, (more expensive) • Multiplexed bus, (shared lines for data/addr/control) • More complexity, (does not guarantee better bandwidth) • Block Transfers • Latency will increase, (the time we wait for access)

  11. Split Transaction Protocol When we don’t need the bus, release it! • Improves throughput • Increases latency and complexity Master Slave Master requests bus ReadReq Ack No one requests bus Wait for Data Slave requests bus DataReady Ack

  12. Bus Arbitration • Bus Master, (initiator usually the CPU) • Slave, (usually the Memory) Arbitration signals • BusRequest • BusGrant • BusPriority • Higher priority served first • Fairness, no request is locked out

  13. Arbitration Protocol • Daisy Chain, (VME bus) • Simple (but limited speed, must pass higher priority devices) • Fairness must be implemented by the devices Pri 4 Pri 3 Pri 2 Pri 1 BusRequest

  14. Bus Arbitration • Centralized • Many request/grant lines • Complex controller, may be a bottleneck • Self Selection • Many request lines • The one with highest priority self decides to take bus • Collision Detection (Ethernet) • One request line • Try to access bus, • If collision device backoff • Try again in random + exponential time

  15. Direct Memory Access (DMA) (2) RAM CP0 2nd level Cache IM DE EX DM 1st level Cache TLB We want to move data from HD interface to RAM (1) HD Interface Why go all the way to the CPU (1) and back to the memory bus (2)

  16. Direct Memory Access • DMA Processor • 1) Generates BusRequest, waits for Grant • 2) Put Address & Data on Bus • 3) Increase Address, back to 2 until finished • 4) Release Bus • Generates interrupt only • When finished • If an error occurred

  17. DMA and Virtual Memory • If DMA uses Virtual address it needs to pass a TLB • Go through the CPU’s TLB (no good) • A TLB in the DMA processor (needs updating) • If DMA uses Physical address • Only transfer within one Page • We give the DMA a set of Physical addresses • (local TLB copy)

  18. DMA and Caching • INCONSISTENCY problem • We change the RAM contents, but not the cache • We write to HD but the RAM holds “old” information • Routing All DMA though CPU • No good, spoils the idea! • Software handling of DMA • Cache: Flush selected cache lines to RAM • Cache: Invalidate selected cache lines • TLB/OS: Do not allow access to these pages until DMA finished • Hardware Cache Coherence Protocol • Complex, but very useful for multi processor systems

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