Concentrator Card Review

1. Concentrator Card Review 22nd March 2006 Concentrator Card Review: Greg Iles

2. Last processing stage before calorimetry data sent to Global Trigger 9U VME64x card 2 DPMCs mounts for electron-leaf cards 2x3 Samtec cables to interface to jet-wheel cards 1 DPMC mount for Global Trigger interface What is the concentrator ? Concentrator Card Review: Greg Iles

3. Jet interface Arrives from 2 x wheel cards via high speed Samtec cable assemblies 240 LVDS signals from each Wheel card (40 MHz DDR -> 80Mhz) 190 for trigger path 34 for control & readout 2 for clk 4 for jtag 10 not connected at present Electron interface Arrives from 2 x leaf dual PMC cards mounted on concentrator card Only 206 out of 386 I/O used) 160 for trigger path 40 for control & readout 2 for clk 4 for jtag Incoming data Concentrator Card Review: Greg Iles

4. Global Trigger interface GT receives 7 cables (2 unidirectional SerDes channels per cable) Each channel driven by NatSemi DS92LV16 Takes 16 bit parallel data at 80MHz. Adds 2 bits. Transmits at 1.44 Gb/s Require 2 bits for powerdown/sync 252 signals (7 x 2 x 18) Require 1 cable for loopback testing Generates 16 bits parallel data Require 4 bits for lock, refclk, powerdown and recovered clk 40 signals (1 x 2 x 20) NatSemi chips do not have JTAG Could use local loopback to test data lines only. Require 2 bits for outenable and local loopback on all chips 44 signals ((14 x 2) + 16 Mounted on dual PMC All 380 I/O connected, Require at least 292 signals, perhaps 336 Slink Signals connect to VME J2 and hence to ECAL transition card Outgoing data Concentrator Card Review: Greg Iles

5. Processing Two Xilinx Virtex4 FPGAs XC4VLX100-FF1513 Must concentrate large amount of data Choose package with most I/O Integrated differential termination makes layout simpler High speed I/O provide reserve capability Communication Xilinx Virtex2 FPGA XC2V3000-BF957 Robust in 3.3V enviroment VME 64x interface Slink TTCrx Ethernet PHY & USB for future Elec FPGA Isolated Electrons Non-Isolated Electrons Energy Sums Jet Counts Jet FPGA Forward Jets Central Jets Tau Jets Implementation Concentrator Card Review: Greg Iles

6. Trigger All paths 40 MHz DDR -> 80MHz Electron data 2 x 160 Single Ended Via J11, J12, J21, J22 Electron η+ data from Leaf DPMC 1) Iso Elec 2) Non-Iso Elec 3) Energy Sum 4) Jet Counts Electron η- data from Leaf DPMC Electron V4 FPGA Sorted Et and jet count 2 x 40 Diff Pairs ** Via Samtec J2 Global Trigger DPMC 7 x dual channel Serdes links 80 Single Ended Jet η+ data from Wheel Card 2 x 180 Single Ended Via fully populated 1/2 DPMC Jet V4 FPGA Jet η- data from Wheel Card Sorted & unfinished jets 2 x 150 Diff Pairs Via Samtec J1 & J3 5) Forward Jet 6) Central Jet 7) Tau Jet ** Indicates schematic change required Concentrator Card Review: Greg Iles

7. Jet data sent to ‘”Jet’” FPGA Top 4 rank of central, forward and tau jets. Hence 12 objects 12 sorted jets (min 14 bits each) 5 bits phi 3 bits eta (no need for sign) 6 bits rank 12 unsorted jets (min 11 bits each) 5 bits phi 0 bits eta (events in the middle) 6 bits rank Total = 150 signals @ 80MHz 300 bits Available = 150 signals @ 80MHz Jet data sent to “Elec” FPGA Missing Et (25 bits) 12 bits Etx and Ety 1 bit overflow Et jets (13 bits) 12 bits mag 1 bit overflow Jet count (30 bits) 5 bits for 6 eta/phi regions Total = 34 signals @ 80MHz 68 bits Available = 40 signals @ 80MHz Signal counts: Jet-Wheel input All numbers for single jet-wheel card Concentrator Card Review: Greg Iles

8. Signal counts: Elec-Leaf input • Electron data sent to ‘”Elec” FPGA • Top 4 rank of isolated and non-isolated electrons (min 14 bits each) • 8 electron objects • 5 bits phi • 3 bits eta (no need for sign) • 6 bits rank • Missing Et (25 bits) • 12 bits Etx and Ety • 1 bit overflow • Et electrons (13 bits) • 12 bits mag • 1 bit overflow • Total = 75 signals @ 80MHz • 150 bits • Available = 160 signals @ 80MHz All numbers for single elec-leaf card Concentrator Card Review: Greg Iles

9. Control & Readout 40 MHz DDR -> 80MHz Slink VME TTCrx Clock Control FMM USB Ethernet 1) Iso Elec 2) Non-Iso Elec 3) Energy Sum 4) Jet Counts Electron η+ data from Leaf DPMC 2 x 40 Single Ended Via J23 Electron η- data from Leaf DPMC Electron V4 FPGA Comm V2 FPGA 2 x 32 Single Ended Jet η+ data from Wheel Card Jet V4 FPGA 2 x 34 Diff Pairs ** Via Samtec J2 V2 driving LVDSEXT Jet η- data from Wheel Card 5) Forward Jet 6) Central Jet 7) Tau Jet V2 V4 DCI LVDS requires 62.5mW per pair 100 100 ** Schematic change required Concentrator Card Review: Greg Iles

10. Readout Max slink sustained rate = 200 MB/s Assume no source generates more than 100MB/s 10bits @ 80MHz Control Serial VME 2bits L1A 1bit Serial Fast Commands from TTC B channel (e.g. resync) 1bit AsyncReset 1bit Serial FastFeedback 1bit Total Required = 16 signals Minimum available = 32 signals Signal counts: Control & Readout Concentrator Card Review: Greg Iles

11. Floorplan Concentrator Card Review: Greg Iles

12. High speed serial links Susceptible to power supply noise SerDes power will be provided by local linear regulators Mounted on DPMC If design revision necessary cost and turnaround time should be substantially less. PCB layout concerns dominate Must do a reasonable job of length matching Retain option for increased speed Must match as pairs More time consuming that SE bus matching Once again, budget extra time for layout Virtex 4 FPGAs New devices Highly desirable due to enhanced I/O Conservative design requirements Likely requires .0201 decoupling cap scheme Blind/buried vias, small drill diameters .008” used extensively on leaf card Straightforward, but physically large design Layout may be longer than estimated Risk of error or omission higher due to design size Design issues Concentrator Card Review: Greg Iles

13. Design enhancements (I) • Jet FPGA-Wheel card interface • Hook up remaining 10 LVDS pairs on Samtec connector to Jet FPGA • However all I/O currently used. • Take from either: • Jet-Elec Interconnect. • Currently 80 signals • DPMC used for GT interface • 380 I/O connected, • Require at least 292 signals • Require 336 to extend board testability Concentrator Card Review: Greg Iles

14. Improve power supply system Datel LSM-10A D5 switchers generate < 50mVpp ripple Move to Texas Inst. PTH08T240W < 10mVpp ripple (possibly due to large output caps) AutoTrack for synchronised power up SmartSync allows switchers to be phased Fuses Test power supply before powering up rest of board Method to measure current Current power supply based on Datel LSM-10A switcher, 10A 2 x 1.2V 1 x 1.5 V 2 x 2.5V TPS759XX linear, 7.5A 3.3V & 1.8V from 5V Current limited by thermal load Warning clk distribution requires 3.3V and the QPLL 2.5V Design enhancements (II) Concentrator Card Review: Greg Iles

15. Testing • Connectivity test • Can test connectivity of ~80% of board with either JTAG or custom firmware. • Samtec connections • Loopback with production cables • PMC sites • Matt’s DPMC test board? • FPGA-FPGA connnections • Insitu tests • VME, Slink etc are probably best tested by real life using final firmware in test mode • E.g. for VME by writing/reading register many times • Alternative is that you need a dedicated JTAG loopback system. • Unfortunately doesn’t check all connectivity. • Danger is that in 6 months time you find VME Address bit 22 doesn’t work Concentrator Card Review: Greg Iles

16. Schematics complete Minor revisions likely Missing clk/jtag on Samtec J2 Missing AsyncReset from front panel / FPGA done pin. Need to add FPGA decoupling when Wheel card design returns Ready for PCB layout group to start work as of end of last week. Work has yet to start Cannot verify, but I belive original estimate was 7 weeks Design has gained an extra FPGA, but lost SerDes links. Firmware Started firmware development. Checking no problems on clock placement Status Concentrator Card Review: Greg Iles

17. Thanks to Magnus & Matt for support as I struggle to become healthy Concentrator Card Review: Greg Iles