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CFO Compensation in Frequency Domain

CFO Compensation in Frequency Domain. Presenter: Pin-Hsun Lin Advisor: Prof. Tzi-Dar Chiueh Date: Aug. 18 th 2003. Outline. Motivation Time-delay in a loop What are the impacts of delay in a loop? How the error performance degrades with the prolonged settling time?

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CFO Compensation in Frequency Domain

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  1. CFO Compensation in Frequency Domain Presenter: Pin-Hsun Lin Advisor: Prof. Tzi-Dar Chiueh Date: Aug. 18th 2003

  2. Outline • Motivation • Time-delay in a loop • What are the impacts of delay in a loop? • How the error performance degrades with the prolonged settling time? • Under what condition the conventional method is improper? • Loop filter design for a stable system • With/without consideration of phase error variance • Preliminary remedies • Frequency domain compensation • Circular convolution, interpolator, rotation • Conclusion

  3. Motivation • In the 802.11a project the time domain CFO • tracking is said to be unstable since there’s a • large delay (FFT block) • Find out how the delay affects the burst • communication and how to solve the problem • caused by the effect efficiently.

  4. Some causes of the delay in feedback loop in a communication system include: • Pipeline registers • Latency of signal processing blocks: • FFT, CFO estimation, TFO estimation, etc. Model of delay in a loop Example: CFO compensation of OFDM and CP-SC system Up to 2 OFDM symbols delay If symbol based estimator is used 2 FFT NCO 1 CFO Estimator NCO ACC ACC

  5. Impacts of delay in a loop: Delay in a loop increases The optimal natural frequency is decreased [1] The error variance increases [1] The settling time increases [3] [4]. Trade-off

  6. is the laser line-width Impacts of delay in a loop: the model of loop with delay [1][2] KD Delay τ Close loop transfer function K0/S F(s) is the LO signal power

  7. Impacts of delay in a loop: the increased error variance and the decreased optimal natural frequency [1][2] Optimal loop design No modification according to the loop delay Bit rate=565Mbps

  8. How the error rate performance degrades with the prolonged settling time? Length of training sequence Accuracy of coarse synchronization Delay in a loop The length of settling time Error rate performance

  9. Under what condition the conventional method is improper? If the previous relationship is valid, then under the following conditions the conventional methods are improper: • In burst communication (not such long time for convergence) • When training symbol is very short like 802.11a

  10. Loop filter design for a stable system:w/o consideration of phase error variance [3] Analytical method: The stable region is enclosed by: M=0 M=1 M=2 (only for 2nd order loop) M is the samples of delay

  11. Loop filter design for a stable system:w/o consideration of phase error variance [4] Numerical method: • Replacing z=exp(u+jv) • into the denominator of • the loop transfer function. • scan u>0 and v=0~2*pi • The region doesn’t cover • by the spirals is the stable • region as the right figure • shows. M=1, 2nd order loop

  12. Then F (S) stabilizes the loop iff: Loop filter design for a stable system:with consideration of phase error variance [5] • Given delay want to find an F(s) that minimizes the phase error variance: 1. 2. where Q is any stable proper and rational function. 3. Then find Q by minimizing . (The solution is complicated so isn’t shown here.)

  13. Preliminary Remedies

  14. CFO compensator FFT CFO Estimator Compensate the error in frequency domain Design criterion: • The latency of the frequency domain compensator • must be smaller than the time domain one. • The additional complexity must be moderate.

  15. Time domain compensation: Frequency domain compensation: Frequency domain compensation: Circular convolution • Time domain rotation is equivalent to frequency domain circular convolution. A is circulant with 1st row=

  16. Frequency domain compensation: Circular convolution (cont’d) Truncation

  17. Required SNR degradation Frequency domain compensation: Circular convolution (cont’d) • The length to be truncated can be determined by: • The computational complexity can be further optimized by the Chinese remainder theory (CRT) and the latency can be further improved. • Low latency architecture is under researched.

  18. Interpolator [6] 1st stage 2nd stage N N NP NP Zero padding P interpolator FFT CFO Estimator

  19. Interpolator (cont’d) CFO normalized to the sub-carrier spacing • The constant BER degradation • between no CFO and the cubic • interpolator may be because • not enough information is • included to do the compensation. • The sufficient and necessary • conditions for the usage of • interpolator is needed be • investigated. ~0.001 ~0.001

  20. Rotation [7] • Rotation is the easiest method with the lowest latency and the worsterror performance. • When CFO is small,the effect of CFO can be considered as a phase rotation. • the residual CFO can be compensated by frequency domain rotation. • The ICI can’t be removed by the rotation. • The resulted SNR degradation is related to how accuracy the coarse synchronization can achieve.

  21. OFDM D≈ SC Rotation (cont’d) • Given BER, we can get SER by the following • approximation for M-ary modulation : • Using the SER we can get the corresponding SNR. With • the SNR and the following approximation we can get the • SNR degradation (SINRnon-ideal-SNRideal in dB). R is the clock rate

  22. Conclusion • The impacts of delay in a loop were introduced. • 3 Loop filter design methods for a stabilize a time-delay system were introduce. • 3 frequency domain compensation methods were introduced Future work: • Research the relationship between the error rate • performance degradation and the prolonged settling time. • Validate the sufficient and necessary conditions for the • usage of interpolator. • Merge the circular convolution and the interpolator and find • a low latency architecture.

  23. Reference • [1] M. A. Grant, W. C. Michie and M. J. Fletcher, “The performance of optical phase-locked loops in the presence of nonnegligible loop propagation delay,” IEEE Journal of Lightwave Technology, Vol. 5, No.4, April, 1987, pp. 592-597. • [2] S. Norimatsu and K. Iwashita, “PLL propagation Delay-time influence on linewidth requirements of optical PSK homodyne detection,” IEEE Journal of Lightwave Technology, Vol. 9, No.10, Oct, 1991, pp. 1367-1375. • [3] J.W.M. Bergmans, “Effect of loop delay on stability of discrete-time PLL, “Circuits and Systems I: Fundamental Theory and Applications. IEEE Transactions on, Volume: 42 Issue: 4, April 1995, pp. 229 -231 • [4] A. D. Gloria, D. Grosso and M. Olivieri and G. Restani, “A novel stability analysis of a PLL for timing recovery in hard disk drives,”Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on , Volume: 46 Issue: 8 , Aug. 1999 pp. 1026 -1031 • [5] O. Yaniv and D. Raphaeli, “Near-optimal PLL design for decision-feedback carrier and timing Recovery,” IEEE Trans, Commu. Vol. 49, No. 9, Sept 2001, pp. 1669-1678 • [6] M.Luise, M. Marselli and R. Reggiannini, “Low-complexity blind carrier frequency recovery for OFDM signals over frequency-selective radio channels,”Communications, IEEE Transactions on, Vol. 50, No. 7, July 2002 pp. 1182 -1188 • [7] T. Pollet, M. V. Bladel and M. Moeneclaey, “BER sensitivity of OFDM systems to carrier frequency offset and Wiener phase noise,” IEEE Trans, Commu. Vol. 43, No. 2, Feb 1995 • [8] J. R. Barry and J. M. Kahn, “Carrier synchronization for homodyne and heterodyne detection of optical quadriphase-shift keying,” IEEE Journal of Lightwave Technology, Vol. 10, No.12, Dec, 1992.

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