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Status of 3D-IC Technology Research and Development in Japan

Status of 3D-IC Technology Research and Development in Japan. Masahiro Aoyagi Nanoelectronics Institute ( NeRI ) National Institute of Advanced Industrial Science and Technology (AIST). Outline. Introduction of 3D LSI Chip Stacking Technology National R&D Project

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Status of 3D-IC Technology Research and Development in Japan

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  1. Status of 3D-IC Technology Research and Development in Japan Masahiro Aoyagi Nanoelectronics Institute (NeRI) National Institute of Advanced Industrial Science and Technology (AIST)

  2. Outline • Introduction of 3D LSI Chip Stacking Technology • National R&D Project • Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology • 3) AIST R&D Activities

  3. IPBlock Comparison of System Integration Technology System on Chip SOCTechnology 3D LSI Chip Stacking System Technology System in Package SIP Technology IPChip LSIChip Package IPChip Through Si Via TSV I/OBuffer & ESDCircuits Interconnections between IP Blocks with On-Chip Wiring Interconnections between IP Blocks with In-PKG Wiring Interconnections between IP Blocks with TSV Internal Low Signal Level Connections in LSI External High Signal Level Connections in PKG Internal Low Signal Level Connections between Chips High Performance & Low Power Dissipation Low Performance & High Power Dissipation High Performance & Low Power Dissipation Increase of Design & Manufacturing Cost Reduction of Design & Manufacturing Cost Reduction of Design & Manufacturing Cost

  4. Future Consumer Products with 3D LSI Chip Stacking System Cutting Edge Healthcare/Bio Futuristic Robots Capsule endoscopes, artificial organs, behavior management monitors, smart shirts for medical care etc. AI robots, neuro-computers, household robots Laptop Super Computers Advanced Futuristic Consumer Electronics Laptop Super Computers Simultaneous translation capability TV-equipped mobile phones Wall-mounted TVs enabling viewing of foreign films in Japanese Ultra High-Performance Games Combination of MEMS, analog, logic and memory chips etc. High-performance next-generation game machines Ultra high-speed, high-precision cameras Auto-Pilot for Cars Ubiquitous Computing Human Interfaces Automatic travel to destination and automatic driving features Speech recognition Virtual keyboard Wearable computers, sensor networks

  5. National R&D Project:Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology

  6. National R&D Project: Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology Joint Research and Development System The New Energy and Industrial Technology Development Organization 6

  7. Research Overview Project Schedule Project Name: “Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology” Research Topics: 1) High-Density 3D-Integration Technology for Multifunctional Devices 2) 3D Reconfigurable Device Technology 3) 3D Integrated RF Device Technology for Multi-band Communication Systems Main Project term: FY2008 ~ FY2012 (5 years) Research Fund: FY2008 ≒ 850 million yen FY2009 ≒ 2.3 billion yen 2012- 2008 Main Research (Dream Chip) 2007 Preliminary Research Technical Survey 2006

  8. Member Companies of the Project and its Organizations ~FY2012 Research Partners (9 Institutions) ASET (Industrial consortium: 21 companies) Universities -(NEC Electronics) -(Renesas) Renesas Electronics -Elpida Memory -Toshiba -Rohm Device Manufacturers -Kyoto University -Shizuoka University -University of Tokyo -Tohoku University -Toyama Prefectural University -Shibaura Institute of Technology -Meisei University -Tokyo Institute of Technology Basic Fundamental Research -NEC - Fujitsu -Sharp -(Nac Image Technology) -IBM Japan -Panasonic -Hitachi - Denso Electronic Equipment Manufacturers Joint Research Research Institute -(Advantest) -(Dai Nippon Printing) -Ibiden-Toppan Printing -(Zycube)-(Tokyo Electron) -Shinko Electric -(Yamaichi Electronics) Materials/ System Manufacturers etc. AIST （The National Institute of Advanced Industrial Science and Technology）

  9. ⑤-Ａ　R&D on Architecture and Design Technology for 3DReconfigurable Device Technology 7 8 ⑤-BR&D on 3DIntegration Technology for3DReconfigurable Device Technology Development Themes 1 ①-AR&D on Design Environment Technology 2 ①-Ｂ R&D on Interposer Technology 3 ②-Ａ R&D on Chip Test Technology 4 ②-Ｂ　R&D on Cooling and Stacking/Bonding Technology 5 ②-Ｃ　R&D on Thin Wafer Technology ③-Ａ　R&D on Demonstration Devices Design and Process Development 6

  10. Driver chip mounted ①-ＢR&D on Interposer Technology （1B1）　R&D on Signal Integrity(SI) Technology and Power Integrity(PI) Technology -1) Design and fabrication of I/F chips (driver, serial-parallel conversion) -2) Design and fabrication of prototype interposer for high-speed I/O driver 　　　　* Prototyping of surface mount, embedded component, Si interposer 　　　　* Prediction of achieving 20Gbps SI by improving master design of simulation base - 3) Design and fabrication of of power noise evaluation system using FPGA Example of SI improvement by countering Z0 mismatch at via Prototype interposer for high-speed driver IC Power noise evaluation system Simulation 20Gbps transmission impossible FPGA Simulation 20Gbps transmission possible

  11. ②-Ａ R&D on Chip Test Technology Wafer Probe Concept Specifications: 300,000 electrodes 15Gbps5kA,10kW/Wafer (2A1: Non-contact probing) (2A3: Non-contact connector) 被測定ウェハ data(Tx) data(Tx) data(Rx,150um2) data(Rx,80um2) (Measurement situation) data(Rx) (Measurement situation) data(Rx,100um2) (Transmission waveforms <1Gbps>) (Transmission waveforms <1Gbps>) X direction Y direction (Shape prototype appearance) Transmission speed [Mbps] Transmission speed [Mbps] (Permissible position accuracy <±30um @1Gbps>) In case of data(Rx,80um2) -Basic operation of C coupled receiving circuit -Signal transmission exceeding 500Mbps -Basic operation of C coupled receiving circuit -1Gbps signal transmission

  12. ②-BR&D on Cooling and Stacking/Bonding Technology (2B1)-1 R&D on Thermal Evaluation and Cooling Technologies 　・Design Technology Optimization for High thermal Transfer of Chip stacking Structure 　・High Accuracy Thermal Characteristics Evaluation Technology for Micro Structure and Ultra Thin wafer bonding Structure 　・Micro Structure -High Accuracy Simulation Technology 　・High Thermal Conductivity Space Filling Material 　・Propose a Optimum Thermal Design Criteria for the Integrated Structure 　・Small and High Efficiency Cooling Structure Modeling Individual Bonding & Air Thermal Resistance Compound (Bonding & Air) Thermal Resistance Si 両者の温度分布（熱抵抗）は大きく異なる Simulation(Temperature distribution) (2B1)-2R&D on the Evaluation and Analysis Technologies for the Stacking/ Bonding 　・ Highly Reliable Bonding Technology between Chips of Multiple Micro Bondings (Bump Diameter to be less than 5μmand Number of Bumps to be more than 10,000) 　・ Non Destructive Inspection and Evaluation/ Analysis Technologies for Submicron Failures ・ Optimum Design Criteria for High Yield Integration Process/Structure/Material

  13. ③-Ａ　R&D on Demonstration Devices/Device Design Desirable structure and dimensions were determined through design studies in FY2008 TSV 35μm 35μm pitch TSV 5μm CDS：Correlated Double Sampling 30μm Sensor chip ※ CDS chip 30μm Prototype vision system for FY2010 10～30μm ADC Chip 70μm pitch Interface chip 110μm pitch Organic substrate interposer Image sensor layer This large scale frame memory is not included in the plan for FY2010 CDS S/H layer Interposer Reconfigurable processor Memory ADC layer Sensor/ADC Frame memory Processor

  14. AIST R&D Activities in3D LSI Stacking Technology

  15. National Institute of AIST National Institute of Advanced Industrial Science and Technology (AIST), led by President Dr. Nomaguchi, is funded by Japanese government.  AIST is a rather new research organization established in 2001.  Headquarters of AIST are located in Tsukuba and Tokyo.  AIST has over 50 research units in various innovative research fields.  About 2500 research scientists (about 2000 with tenure) and well over 3000 visiting scientists, post doctoral fellows and students are working in AIST. Tsukuba Research Center

  16. Fundamental R& D of 3D LSI Chip Stacking System Technology R & D in AIST Fine Bump Joints Interfilling Layers TSV for Signal TSV for Power Electroless Plating Bridge Connection Thin CMOS-LSIChips External Interface (Electrical & Optical) Power Delivery LC Embedded Interposer for High-speed Signal & Power Delivery ・Fine Micro Bump Joint Technology ・LC Embedded Interposer Technology ・Heat Spreading Technology

  17. 3D R&D Projects in Nanoelectronics Institute 1） High-Density Wiring Interposer with High-Speed Signal Transmission and Power Delivery for 3D LSI Chip Stacking Tehcnology （NEDO R&D Projects: Electronic System Integration, Dream Chip etc.） 10micron multilayer wiring、20Gbps high-speed transmission line, passive device embedded interposer, power delivery network evaluation system etc. 2) 10 micron pitch micro bump connection（NEDO R&D Projects: Energy Saving etc.） 10-5micron fine bump formation, submicron accuracy flip-chip joint 3) 3D LSI Chip Stacking Technology with High Thermal Conductive Layers （NEDO R&D Projects: Energy Saving etc.） Hot Spot Suppression with TSV and High Thermal Conductive Layers 4) Energy Efficient Multi Core Architechture with 3D LSI Chip Stacking Technology （NEDO R&D Projects: Energy Saving etc.） Multi Bus Interface with High Pin Count Chip-to-Chip TSV Connection

  18. Fine Pitch Fine Bump Connection Technology

  19. 15 10 mm 5 0 10 15 20 25 30 0 5 mm 15 10 mm 5 0 10 15 20 25 30 0 5 mm 15 10 mm 5 0 10 15 20 25 30 0 5 mm Shape of Fine Bumps: Electroless Au Plating Bath XG 5mmf 10mm 10mmf 10mm 20mmf 10mm

  20. CPW Test Device for Fine Bump Connection Bump joint 2 CPW transmission line Bump joint 1 Open end Contact pad Transmission Line Design: Coplanar Waveguide Structure ・Specific resistance 1000Wcm high resistive Si ( er=12 , h=380 mm) ・Wiring material is Cu Margin for bump position shift signal line widthw=22 mm line thicknesst=3 mm, line spacingg=18 mm Characteristic Impedance Z0 = 50 W Several g values are prepared for fabrication tolerance .

  21. Fine Au Bump on CPW Transmission Line Device Substrate Cu Coplanar Waveguide 30mmpitch，10mmf，10mm height Aubumps 30mmpitch，20mm□，3mm height Aupads bumps ~ Bump height uniformity well controlled on Cu wiring

  22. Cross sectional of daisy chain Cross Sectional of bump joint on signal lines Cross Sectionals of Fine Bump Connections Pretreatment: O2 Plasma Bonding Condition: Temperature 375℃ Load17N (1.5g per bump) Confirmed electrical properties of bump joints

  23. High Speed Signal Transmission Characteristics through Fine Bump Connection Only transmission line (Z0 :52 W) Through two bump joints (Z0: 56 W) 10Gbps 10Gbps 92% opening Achieved clear eye diagram for 10Gbps signal Little effect of bump joints

  24. Passive Device Embedded Interposer for 3D LSI Stacking

  25. 3D LSI Stacking System High Performance Low-Power LSI System with Ultra High Pin Count TSV Connections Internal Parallel Bus （>1K bit、>500Mbps） Low-Power Operation with Ultra High Pin Count Parallel Signal Transmission External Serial I/F （64bit、16Gbps） Power Voltage Deviation（Large di/dt） Embedded Decoupling Devices （Core Power：<3%、I/OPower：<5%）

  26. Passive Device Embedded Interposer TEG Comparison of Decoupling Capacitor Performance with Embedding Method ・TEG Designed With Three kinds of Embedding Method (SMT, Organic, Silicon)・TEG Size: 20mm□ , Embedding Area: Central10mm□ , Same Probe Pad Layout ・Capacitor Values: 1~3mF Device Embedding Method FabricatedTEG Interposer TEG Design A-A’ Cross Section Capacitor Embedding Area T11 Chip C Mounted on Reverse Side T21 T1 20mm T2 T22 Z11 Contact Probe Pads T23 A A’ T3 Z21 10mm T4 T24 T25 T5 T15 Measurement Contact Probe Pad After Dicing

  27. Wideband Ultra-Low Impedance Measurement System Connected Seamlessly Two Kinds of Impedance Analyzers into One System Capacitor Embedded Interposer 10Hz～40GHz Wideband Ultra-Low Impedance Measurement System with Two Impedance Analyzers Seamlessly Connected Wideband Widerange Accurate Impedance Measurement & Evaluation Technology Ultra Low Impedance Measurement System (Upper：8722ES, Lower：P4800)

  28. Heat Spreading Technology with High Thermal Conductive Layers

  29. Heat Spread Technology with High Thermal Conductive Material Heat Spot Heat Sink Cu TSV Thin LSI Chip Heat Spreader Interposer Introduction of New Heat Spreader with High Thermal Conductive Materials Heat Spot Suppression

  30. Thermal Management Evaluation Using IR Imaging Hot Spot Test Device Overlap Image IR Image Hot Spot Emulation Test Device Chip Carrier 9 Heater Devices （10х10 mm） IR Video Image 180mm/pixel 8mm/pixel Ring Oscillator

  31. Hot Spot Problem in Thin Si Substrate Micro heater device Chip size : 3×3mm Heater size 1×1mm Ambient temperature: 23˚C Heating value: 0.3W Thickness:380 µm Thin substrate:100 µm Max. 45℃ Max. 119℃ The thermal dispersion is enough and there is no hot spot. There is a hot spot! The hot spot is occured in thin Si substrate.

  32. Multilayer Nanofilm Stack Si:5nm C:7nm Si:5nm ・・・ B Structure18cycle Si:5nm C:7nm Si Buffer layer:20nm C:7nm Si:5nm ・・・ B Structure(thickness ：507nm) 10µm Si:5nm C:7nm Si buffer layer:20nm C:7nm Si:5nm AStructure (Thickness：492nm) ・・・ C:7nm Si:5nm Wafer Cross sectional TEM imageof multilayer nanofilms

  33. Crystallinity of multilayer nanofilms • Raman spectroscopic analysis FWHM of G-peak :119cm-1 *FWHM of G-peak at single carbon layer: 112cm-1 → The thermal conductivity of multilayer nanofilms is 800~1000W/mK

  34. Hot Spot Suppression by Nanofilm Back Coating Micro heater device Chip size : 3×3mm Heater size 1×1mm Ambient temp.: 23˚C Heating value: 0.1W Transient behavior of temperature at central part in hot spot

  35. Low Power Multi Core Architecture with 3D LSI Stacking

  36. 3D LSI Chip Stacking System Technology IP Chip IP Chip IP Chip IP Chip Inductive/ Capacitive/ Electro-magnetic Inter-connection PKG Wiring & Solder Ball Inter-connection TSV & Micro Bump Joint Inter-connection Optical Inter- connection Z Direction Connection of Optical Method Z Direction Connection of Wireless Method Z Direction Connection of TSV & Micro Bump Joint Z Direction Connection of PKG Level Signals：10-1000 Signals ：10-1000 Signals ：100-10000 Signals ：10-1000 Speed: 1~100Gbps Speed: 10G~1Tbps Speed: 100G~10Tbps Speed: 1~100Gbps Low Cost System Robust Easy Maintenance System High Performance System Ultra High Performance System

  37. COOL System –Ultra Low Power Flexible & Extendable Hardware NEDO 『Energy Saving Technology R&D』Collaborative Research with Tops Systems Corp. • Target：　Ultra Low Power System・Small Volume Production・Short System Development Period • COOLChip : Ultra Low Power Heterogeneous Multi Chip 【3D LSI Stacking Emulation FPGABoard】 • Reduction of Power Consumption with 1/10 Clock Frequency Heterogeneous Multi Core/Multi Chip • COOL Interconnect : Ultra Low Power Parallel Bus Interface 【Interface Test Chip】 • Scalable Connection with Heterogeneous Chips • COOL Software ：　Functional Distribution Processing • Improved signal processing efficiency with KPN Model 情報処理学会　　　２０１０．１２．６ 組込システム研究発表会（熊本大）で発表 電子情報通信学会 ２０１１．３．２ VLSI 設計技術研究会（沖縄）で発表予定

  38. ３DLSI Chip Stacking Process Linewith Minimal Fab System

  39. Minimal LSI Fab System Proposed from AIST Type1: Mega Fab System 500 Billion Yen Wafer 1/1000 12” 3m 200m Type2: Minimal Fab System 1/1000 500 Million Yen Wafer0.5” Without Clean Room 3m 30cm

  40. 30cm Minimal Coating/ Developing Minimal Lithography Minimal Cleaning minimal PLAD minimal PLAD minimal PLAD minimal PLAD minimal PLAD minimal PLAD minimal PLAD Minimal Bumping Minimal PE-CVD Minimal Deep Etching Minimal Wafer Bonding Minimal Wafer Thinning Minimal Testing Minimal Cu Via Filling R&D of Minimal LSI&3D Process Equipment Minimal Fab Consortium PLAD：Particle Lock Air-tight Docking LSI Production/ R&D FY-2010 FY-2011 Minimal Plasma Etching Minimal Supptering Deposition Minimal Wet Etching Minimal Furnace Minimal ･･･ minimal PLAD minimal PLAD minimal PLAD minimal PLAD minimal PLAD minimal PLAD minimal PLAD minimal PLAD Minimal Clean Shuttle Production System ミニマルシャトル 3D LSI Production/ R&D 3D Minimal Fab Consortium

  41. SEMICON Japan 2010 700Visitors in AIST Booth Minimal Fab Equipment Concept Model

  42. Preparation Chamber： Size Reduction Achieved Preparation Chamber 10cm 40cm 15cm 10cm PLAD: Particle Lock Air-tight Docking Dust particles and gases can be isolated. Localized clean space transfer system Minimal Shuttle 新開発･超小型･直線移動機構

  43. Thank you for your attention.

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