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Microarchitecture of Superscalars (5) Dynamic Instruction Issue

Microarchitecture of Superscalars (5) Dynamic Instruction Issue. Dezső Sima Fall 2007. (Ver. 2.0).  Dezső Sima, 2007. Overview. 1 The principle of dynamic instruction issue. 2 Design space. 2.1 Overview. 2.2 Types of issue buffers. 2.3 Operand fetch policies.

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Microarchitecture of Superscalars (5) Dynamic Instruction Issue

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  1. Microarchitecture of Superscalars (5)Dynamic Instruction Issue Dezső Sima Fall 2007 (Ver. 2.0)  Dezső Sima, 2007

  2. Overview 1 The principle of dynamic instruction issue 2Design space 2.1 Overview 2.2 Types of issue buffers 2.3 Operand fetch policies 3Principle of operation of dynamic instruction issue 3.1 Dispatch bound operand fetching 3.2 Issue bound operand fetching 4Implementation of dynamic instruction issue in superscalars 4.1 The introduction of dynamic instruction issue 4.2 Basic implementation schemes 5 Case examples

  3. 1. Principle of dynamic instruction issue (1) Aim: • To eliminate the issue bottleneck of early (first generation) supercalars

  4. 1. Principle of dynamic instruction issue (2) Issue EU EU The issue bottleneck Icache I-buffer Instr. window (3) Decode, Dependent instructions check, block instruction issue issue (a): Simplified structure of the mikroarchitecture assuming unbuffered issue (b): The issue process Figure 1.1: The principle of dynamic instruction issue

  5. 1. Principle of dynamic instruction issue (3) Eliminating the issue bottleneck Dynamic instruction issue (shelving, buffered issue) (a): Simplified structure of the mikroarchitecture assuming buffered issue (shelving) (b): The issue process Figure 1.2: Principle of dynamic instruction issue

  6. 2. Design space of dynamic instruction issue 2.1 Overview Dynamic instruction issue Scope of dynamic instr. issue Instruction issue scheme Layout of the issue buffers Operand fetch policy Types of issue buffers

  7. 2.2 Types of issue buffers RS FP EU RS RS FX FP RS RS FX EU FX EU FP EU FX EU FP EU FX EU FX EU FX EU FX EU Types of issue buffers Issue buffers in the ROB Reservation stations (RS) Individual RSs Central RS Group RSs Power1 (1990) PowerPC 603 (1993) PowerPC 604 (1995) Power4 (2001) Power5 (2004) K5 (1995) K7 (1999), K8 (2003) ES/9000 (1992) Power2 (1993) R10000 (1996) PM1(Sparc64)(1995) Alpha 21264 (1997) Pentium Pro (1995) Pentium II (1997) Pentium III (1999) Pentium IV (2000) Pentium M (2003) Core (2006) Lightning (1991)p K6 (1997)

  8. Dynamic instruction issue Scope of buffered issue Instruction issue scheme Layout of the issue buffers Operand fetch policy Types of issue buffers

  9. 2.3 Operand fetch policies Rs1 Rs2 IB IB Rd Op2/Rs2 Op1/Rs1 Operand fetch policies Issue bound operand fetch policy Dispatch bound operand fetch policy I-buffer I-buffer Decode / Issue Decode / Issue Source reg. identifiers Source reg. identifiers Dispatch Dispatch Reg. file IB IB Issue Opcodes, destination reg. identifiers OC Rd OC Rd Rs1 Rs2 Source 1 operands Source reg. identifiers Source 2 operands Opcodes, destination reg. identifiers Reg. file Issue Source 1 operands OC OC Rd Op1/Rs1 Op2/Rs2 Source 2 operands EU EU EU EU Rd, result Figure 2.1: Operand fetch policies

  10. 3 Principle of operation of dynamic instruction issue IB IB Rd Op2/Rs2 Op1/Rs1 3.1 Dispatch bound operand fetching (1) • Checking the availability of operands I-buffer Decode / Issue Source reg. identifiers Dispatch V Reg. file Opcodes, destination reg. identifiers Source 1 operands Source 2 operands V V V V Issue OC OC Rd Op1/Rs1 Op2/Rs2 EU EU Rd, result

  11. IB IB Rd Op2/Rs2 Op1/Rs1 3.1 Dispatch bound operand fetching (2) • Updating the issue buffers I-buffer Decode / Issue Source reg. identifiers Dispatch V Reg. file Opcodes, destination reg. identifiers Source 1 operands Source 2 operands V V V V Issue OC OC Rd Op1/Rs1 Op2/Rs2 EU EU Rd, result

  12. Rs1 Rs2 3.2 Issue bound operand fetching Checking the availability of operands I-buffer Decode / Issue Source reg. identifiers Dispatch IB IB Issue OC Rd OC Rd Rs1 Rs2 Source reg. identifiers V Opcodes, destination reg. identifiers Reg. file Source 1 operands Source 2 operands EU EU

  13. 4. Implementation of dynamic instruction issue in superscalars 4.1 The introduction of dynamic instruction issue Figure 4.1: The introduction of dynamic instruction issue

  14. 4.2 Basic implementation schemes Basic issue buffer schemes Issue buffers in the ROB Reservation stations (RS) Types of issue buffers Individual RSs Central RS Group RSs Dispatch bound Issue bound Dispatch bound Issue bound Dispatch bound Issue bound Dispatch bound Issue bound Operand fetch policy PowerPC 603 (1993) PowerPC 604 (1995) K5 (1995) PM1(Sparc64)(1995) Pentium Pro (1995) Pentium II (1997) Pentium III (1999) Power1 (1990) Power4 (2001) Power5 (2004) Nx586 (1994) K7 (1999), K8 (2003) ES/9000 (1992) Power2 (1993) R10000 (1996) Alpha 21264 (1997) Pentium IV (2000) Pentium M (2003) Core (2006) Lightning (1991)p K6 (1997)

  15. 5. Case example (1) Individual issue buffers Figure 5.1:The microarchitecture of the Athlon

  16. 5. Case example (1) Individual issue buffers (2) EUs Issue buffers Decoders Figure 5.2: Integer issue buffers of the K8L Source: Malich, Y.„AMD's Next Generation Microarchitecture Preview: from K8 to K8L”, Aug. 2006.

  17. 5. Case example (2) Group issue buffers Figure 5.3: The microarchitecture of the Alpha 21264 Source: Kessler, R.E. et al. .„The Alpha 21264 Microprocessor Architecture”, h18002.www1.hp.com/alphaserver

  18. 5. Case example (3) Central reservation station (1) Figure 5.3: The microarchitecture of the Core processor Source: Kanter, D., „Intel’s next Generation Microarchitecture Unveiled”, Real World Tech., 2006 March 9.

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