Paper presentation: Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation. 2011.04.07 - Presenter: PCLee Design Automation Conference, 2007. ASP-DAC \'07. Asia and South Pacific . Abstract .
2011.04.07 - Presenter: PCLee
Design Automation Conference, 2007. ASP-DAC \'07. Asia and South Pacific
In this paper, we present a method for generating checker circuits from sequential-extended regular expressions(SEREs). Such sequences form the core of increasingly-used Assertion-Based Verification (ABV) languages. A checker generator capable of transforming assertions into efficient circuits allows the adoption of ABV in hardware emulation. Towards that goal, we introduce the algorithms for sequence fusion andlength matching intersection, two SERE operators that are not typically used over regular expressions. We also develop an algorithm for generating failure detection automata, a concept critical to extending regular expressions for ABV, as well as present our efficient symbol encoding. Experiments with complex sequences show that our tool outperforms the best known checker generator.
Efficient Automata-Based Assertion-Checker Synthesis of PSL properties
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation
Assertion Checkers – Enablers of Quality Design
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