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C/VHDL Codesign for LHCb VELO zero-suppression algorithms

C/VHDL Codesign for LHCb VELO zero-suppression algorithms. Manfred Muecke, CERN. Introduction – TELL1. LHCb DAQ Interface Board (EPFL) x300. 36 values * 64 links * 1.1MHz * 10bit = 2.95GB/s. (L1 raw bandwidth w/o protocol overhead). 50.44 cluster * 1.1MHz * 2B = 106MB/s.

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C/VHDL Codesign for LHCb VELO zero-suppression algorithms

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  1. C/VHDL Codesign for LHCb VELO zero-suppression algorithms Manfred Muecke, CERN

  2. Introduction – TELL1 LHCb DAQ Interface Board (EPFL) x300 36 values * 64 links* 1.1MHz * 10bit = 2.95GB/s (L1 raw bandwidthw/o protocol overhead) 50.44 cluster * 1.1MHz * 2B= 106MB/s 2 (4) GBE copper links 64 links @ 40MHz or24 fibers @ 1,2Gbps DSP on 5 Altera Stratix EP1S25..evolving algorithms ..at high data rates Manfred Muecke

  3. System Simulation Framework (C++) DSP on FPGA Motivation – Code Consistency FPGA Design (VHDL) parallel progress -how to guaranteeconsistency? DSP Manfred Muecke

  4. Requirements • to guarantee consistency, one of the two models has to be generated automatically.. ?  VHDL - syntesizeable VHDL - latency as design parameter - efficient resource usage ?  C - fast execution - simple integration/interface Manfred Muecke

  5. Chosen solution Confluence – a synchronous hardware generation language and compiler .cf Confluence Compiler +Code Generator Cf .fnf FNF .vhd .v .c .jhdl .nusmv Manfred Muecke

  6. Confluence Open source project (www.confluent.org) ..functional language for synchronous systems ..written in O’Caml ..runs under Unix/Linux/Cygwin/.. synthesizable VHDL bit- and cycle-accurate C-model .vhd .c Manfred Muecke

  7. Common code base DSP.cf System Simulation Framework (C++) FPGA Design (VHDL) DSP (VHDL) DSP on FPGA (C) X Manfred Muecke

  8. Example -Linear Common Mode Suppression • calculates mean, slope and deviation over 32 samples • 40MHz data stream (x16/FPGA) Manfred Muecke

  9. Measurements Manfred Muecke

  10. Outlook • Implementing further algorithms • Integrating C model in VELO simulation • automated checking of model consistency • language features for DSP • Other solutions/languages? Manfred Muecke

  11. Links LHCb - http://lhcb-public.web.cern.ch TELL1 - http://lphe.epfl.ch/~ghaefeli Confluence - http://www.confluent.org O’Caml - http://www.ocaml.org email - Manfred.Muecke_at_cern.ch Manfred Muecke

  12. Thanks for your attention! Questions? Manfred Muecke

  13. Algorithm  VHDL • IP-based source (Simulink)(Xilinx, TI, Synplicity DSP Synthesis, …)- vendor locked (MathWorks + TI/…)- limited/application-specific IP • Algorithmic source (behavioural synthesis)- on the go (Celoxica, Mentor Catapult C, Forte’s Cynthesizer)- SLDL efforts: SystemC, SystemVerilog-> no RTL control (latency) => as of now, we still have to code in VHDL/RTL (if we care about speed)!! Manfred Muecke

  14. Confluence features • Functional language (recursion) • Dynamic typing (ports adapt) • List type • Vector type -> Hardware • Purely synchronous • Implicit Synchronization (clock, reset, enable) Manfred Muecke

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