1 / 22

XC5200 Series

XC5200 Series. Gate Array. A low cost gate array alternative. XC5200 FPGA Family. Up to 23,000 gates 50MHz system performance Robust feature set Unlimited reprogrammability Pin-Locking Flexibility: VersaRing 5 Volt Devices. XC5200 Series Features.

tayte
Download Presentation

XC5200 Series

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. XC5200 Series Gate Array A low cost gate array alternative

  2. XC5200 FPGA Family • Up to 23,000 gates • 50MHz system performance • Robust feature set • Unlimited reprogrammability • Pin-Locking Flexibility: VersaRing • 5 Volt Devices

  3. XC5200 Series Features • Gate array replacement success since 1995 • World’s fastest 5V FPGA volume ramp • A low cost FPGA/gate array alternative • Low cost, process-optimized architecture • XC5200 Family: 5V, 0.5m • High performance with robust feature set - Carry Logic - 3-state buffers - Cascade Chain - 4 Global Nets - JTAG Logic - Slew rate control

  4. XC5200 Architecture Overview • Architecture Highlights: • VersaBlockTM logic module • VersaRingTM I/O interface • General Routing Matrix (GRM)

  5. Abundant VersaBlock Routing • VersaBlock equals: • Configurable Logic Block (CLB) • 4 identical Logic Cells • 4 3-state buffers • Local Interconnect Matrix (LIM) • 100% local connectivity • Up to 23 in, 8 out • Direct Connects • Result: abundant local routing • Minimizes routing congestion • Granular and symmetrical

  6. XC5200 Configurable Logic Block • Configurable Logic Block (CLB) • 4 Identical Logic Cells • 20 inputs, 12 outputs • 2 5-input functions • Logic Cell (LC0 - LC3) • Function generator, register, & control logic • Independently usable F & FD • Programmable flip-flop or latch • Fast carry logic or cascade chain • Independent feed-through

  7. XC5200 Carry Logic: 4-bit Adder carry out

  8. XC5200 Cascade Chain:16-bit Decoder • Fast implementation of wide input functions • Adjacent CY_MUXes connect to provide cascadable decode logic • Flexible LUT allows general decode, AND and OR cascade chains

  9. XC5200 FamilyEfficient 5-Input Functions • Allows any combination of 2 separate 5-input functions in one CLB • LC0 and LC1 and/or LC2 and LC3 combined with F5_MUX • Unified Library support: • F5MAP or F5_MUX • Efficient 4:1 muxes

  10. Optimizing 5-Input Functions - or - Five input AND using F5_MUX Five input AND using F5MAP Both schematics will result in identical implementations

  11. Implementing 4:1 MUX using F5_MUX • Allows 4:1 muxes in 1/2 CLB

  12. Abundant Routing Resources Local Interconnect Matrix Single Length Lines • 6 Levels of Hierarchy • General Routing Matrix • 10 single length lines • 4 double length lines • 8 longlines per channel • VersaBlock • Local Interconnect Matrix • Direct connects to all neighbors • Logic cell feedthrough Double Length Lines Direct Connects Longlines

  13. XC5200 Global Line Network • 4 global clock buffers • Direct access to all CLB clock pins (CK) • Access to non-clock pins via GRM • Buffers can be sourced by IOB or internal routing

  14. XC5200 TBUF Connectivity • Four TBUFs/CLB • Any CLB output can drive any TBUF • “Weak-keeper” circuit maintains previous state • No pull-ups; use cascade chain for wired functions

  15. VersaRingTM: High Utilization AND Pin Assignment Flexibility • Versatile interface between internal logic and I/O • I/O decoupled from core logic • Incremental edge routing • VersaRing resources • 8 horizontal/vertical longlines • 4 direct connects in/out • 4 double length lines to GRM • 10 single length lines to GRM • 8 single length lines to adjacent VersaRing tile

  16. XC5200 Input / Output Block • Selectable input, output or 3-state • Optional pull-up / pull-down • Dedicated boundary scan logic • 8 mA output sink & source current • 4 global nets • Programmable slew rate control • Programmable input delay line

  17. XC5202 XC5204 XC5206 XC5210 XC5215 Max Logic Gates 3,000 6,000 10,000 16,000 23,000 Typical Gate Range 2-3K 4-6K 6-10K 10-16K 15-23K Logic Cells 256 480 784 1,296 1,936 Flip-Flops 256 480 784 1,296 1,936 Max I/O 84 124 148 196 244 Performance -6/-5/-4/-3 -6/-5/-4/-3 -6/-5/-4/-3 -6/-5/-4/-3 -6/-5/-4/-3 Packages: VQ64 PC84 PC84 PC84 PC84 PQ/VQ100 PQ/VQ100 PQ/VQ100 TQ144 TQ144 TQ144 TQ144 PQ160 PQ160 PQ160 PQ160 TQ176 TQ176 PQ208 PQ208 HQ208 PQ240 HQ240 PG156 PG156 PG191 PG223 XC5200 Family 100% Footprint Compatibility in Common Packages

  18. XC5200 Success Since 1994 2.5M Revenue Units • High Volume Design Wins • Digital camera add-in card • Cable modem • Set-up box • Video game • CD player • Graphics add-in card • 10/100 Mbit Ethernet add-in cards 4Q94 2Q97 2Q96 XC5200 support to year 2005 and beyond

  19. Market Application Volume Consumer-Video Set-Top-Box 150,000 units Consumer-Audio High-end CD Player 25,000 units Consumer-Video Video Game 50,000 units Data Processing PC Add-in Card 250,000 units Data Processing Display Monitor 100,000 units Communication PCS Base Station 25,000 units Communication Modem Card 100,000 units Communication Voice Mail 50,000 units Automotive Shock Absorber Control >100,000 units XC5200 Series Success XC5200 Series shipping NOW in High Volume Markets

  20. Xilinx XC5200 vs. Altera Flex 6K • XC5200 Advantages • Segmented interconnect • Lower power • Five XC5200 devices vs. three 6K devices • More features (flip-flop clock enables, cell feed-through, VersaRing, VersaBlock, etc.) • Altera Flex 6K is a poor copy of the innovative XC5200 architecture

  21. Logic Cell Comparison Feature XC5200 Flex 6K Clock Enable Yes No Direct Feed-through Yes No Independent Logic & Flip-flop Outputs Yes No Clocks per Flip-flop 1:4 2:10 Logic Cells Per Block 4 10

  22. FeatureBenefit Process Optimized - Small die size Architecture - Unlimited reprogrammability - Up to 50MHz performance VersaRingTM I/O - Pin assignment flexibility Interface - Flexibility to change logic without requiring PCB relayout 100% Footprint - Easy density migration within family Compatibility Robust System Level Features: - Fast Carry Logic - High speed arithmetic functions - Dedicated JTAG logic - Eases system-level testability - 3-state buffers - Efficient on-chip bussing - Cascade chain - Efficient wide-input functions XC5200 Benefit Summary

More Related