Team W3: Anthony Marchetta Derek Ritchea David Roderick Adam Stoler

1. Team W3:Anthony MarchettaDerek RitcheaDavid RoderickAdam Stoler Design Manager: Steven Beigelmacher Milestone 3: Feb. 4th Size Estimates/Floorplan Overall Project Objective: Design an Air-Fuel Ratio Controller for a small gasoline engine with low emissions and low cost

2. Status • Design Proposal (done) • Architecture (done) • High Level C Simulation • Behavioral Verilog & Test Bench • Final Algorithm & Major Functional Components • Floorplan & Structural Verilog (done) • Not yet simulated • To be done • Gate Level Design • Component Layout • Chip Layout • SPICE Simulation of Entire Chip

3. Design Decisions (before) • Look-up tables and comparing values for look-up tables programmable. • 7 SRAM blocks (1 8x8, 2 8x1, 4 7x1) • Fixed point Multiplier for decimal numbers • Increment output register to know when multiplications are completed

4. Design Decisions (after) • Look-up tables and comparing values for look-up tables programmable. • 2 SRAM blocks (1 8x10, 1 7x4) • Fixed point Multiplier for decimal numbers (same) • Increment output register to know when multiplications are completed (same) • Only one comparator is needed along with more control logic.

5. SRAM Design • Writing to SRAM • Drive B and ~B with in and ~in • Assert select line • Value will be latched • Reading from SRAM • Assert precharge on positive edge • Assert select on negative edge • Low side will discharge through transistors to GND • High side will remain high • Transistor sizing • T3 must have larger resistance than T1 (narrower transistor) so value won’t be erased on read • Same for T4 and T2

6. SRAM Design • One 7x4 Block for Comparator Values • Sequential accesses for comparison (only 1 comparator) • Results stored in registers • One 8x10 Block for Look-Up Tables • All entries will be 12-bit entries • Done in bit slices for simplified interconnect Comparator Value Table 0 speed 1 2 load Comp Value 3 throttle 4 5 oxygen 6 0 1 2 3 4 5 6 7 8 9 10 11 Bit Number

7. SRAM Layout 360 um Column Decoder R O W D E C 8 x (10x12) Lookup Table 48 um MUX 144 um 144 um Column Decoder R O W D E C 3 um 7 x (4x12) Comparator Table Individual Cell 42 um 6 um MUX

8. Comparator Design For least significant bit: For most significant bit:

9. 12 12 vdd RC Adder Over-flow sign Alternate Comparator Design Subtractor • Look at the sign bit to see which input is greater • This design requires that your inputs and look-up table values be 2C encoded. • Or it requires that you add a sign bit or do a conversion • This would significantly change our design.

10. before Engine Speed 12bit Input Reg Control Logic 8X8 SRAM Look-up Manifold Pressure 12bit Input Reg 2:1Mux 2:1Mux %Oxygen 12bit Input Reg 7X1 L.U. Fixed Point Array Multiplier 8X1 SRAM Look-up Throttle Position 12bit Input Reg 7X1 L.U. 12bit Output Shift Register 8X1 SRAM Look-up 7X1 L.U. 7X1 L.U. OUTPUT

11. %Oxygen 12bit Input Reg Throttle Position 12bit Input Reg after Engine Speed 12bit Input Reg Control Logic Manifold Pressure 12bit Input Reg 7X4 SRAM Comparator Look-up 12bit Register 12bit Register 2:1Mux = < > 3bit register 4:1Mux Fixed Point Array Multiplier 8X10 SRAM Value Look-up 12bit Output Shift Register

12. Floorplan • Basic Parts • FA - 18µm X 11µm • HA - 5µm X 7µm • DFF - 21µm X 20µm • Xor - 10µm X 7µm • These estimates are from downsizing 322 Fall 2002 layouts.

13. 144qndgqtes 11hq 11fq 11fq ……. ha 9FA ha Floorplan • Multiplier 210µm 220µm

14. Multiplier 7X4 SRAM Comparator 8X10 SRAM Floorplan 300µm Registers and control logic 400µm Total area: 120,000µm2 density: 0.13 trans/µm2

15. Metal Directionality

16. Updated Transistor Count

17. Problems • Figuring out how to optimize the comparisons • Optimizing the control logic

18. Questions????