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Progress Report Flash ADC Probabilistic Architecture. Yuta Toriyama. [email protected] August 10, 2012. The design of a variability-agnostic Flash ADC Using small devices and low supply voltages for a low-power low-area design

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Progress report flash adc probabilistic architecture
Progress ReportFlash ADC Probabilistic Architecture

Yuta Toriyama

[email protected]

August 10, 2012


Low power flash adcs

The design of a variability-agnostic Flash ADC

Using small devices and low supply voltages for a low-power low-area design

Architecture / calibration techniques to deal with large amounts of variation

Basic concept: Model each comparator as having a static voltage offset at its input

Low Power Flash ADCs


Probabilistic approach
Probabilistic Approach

  • Architectural design:

    • Allow only certain comparators to be active

    • Turn off power to unused comparators

  • Requirements:

    • Threshold values and indexes of chosen comparators must be monotonically increasing

    • Single 1 output to decoder

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Logic

Encoder

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Network formulation

Represent the entire Flash architecture as a network

Each comparator (or voltage at which it switches) is a node

Network Formulation


Network formulation1

Any path from lowest to highest comparator in this network guarantees a monotonic sequence of active comparators

To find an “optimum” path, assign weights to each edge

Network Formulation


Lp formulation simplex algorithm
LP Formulation & Simplex Algorithm guarantees a monotonic sequence of active comparators

x = vector s.t. xi{edge chosen (1), edge not chosen (0)}

LP can be solved with Simplex Algorithm

Theoretical average-case complexity = O(|V|*|E|)

maximize cTx

s.t.Ax = [1 0 0 . . .-1]T

0 ≤ xi ≤ 1, i

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nodes

arcs


Dijkstra s algorithm
Dijkstra’s Algorithm guarantees a monotonic sequence of active comparators

Solves single-source shortest path problem for networks with non-negative edge weights

Simple implementation complexity = O(|V|2)

Balls (vertices) connected by strings (edges) of different lengths (weights)


Fpga implementations
FPGA Implementations guarantees a monotonic sequence of active comparators

Dijkstra’s Algorithm:

outperforms Simplex in time-to-solution

uses much fewer resources in FPGA implementation than an implementation of the Simplex algorithm


Edge weight assignment
Edge Weight Assignment guarantees a monotonic sequence of active comparators

Calculate the noise power contribution of each arc:

Vj

Ck =

for allk= {1,2,Numarcs}

Vi

di= 4

  • Allows for the inclusion of non-uniform distributions

  • Does not take into account linearity


Look up table
Look-Up Table guarantees a monotonic sequence of active comparators

Currently the encoder output indicates the index for which comparator was toggled

Instead, we would like the output to indicate what analog voltage trips the comparators

Threshold voltages known from DAC measurements taken for foreground calibration


Look up table1
Look-Up Table guarantees a monotonic sequence of active comparators

Add a look-up table at the output of encoder

Values filled in after calibration

Size of memory required ~1kb for # comparators = 1024 (based on number of active comparators after calibration)


New graph formulation
New Graph Formulation guarantees a monotonic sequence of active comparators

Divide threshold voltage axis into L equally-spaced regions

Find one comparator from each region, index of comparators still must be monotonically increasing

Cost = distance from midpoint of each region


New graph formulation1
New Graph Formulation guarantees a monotonic sequence of active comparators

ENOB, linearity improved


Conclusion
Conclusion guarantees a monotonic sequence of active comparators

  • Dijkstra’s Algorithm leads to great improvement in calibration method

  • LUT-based calibration shows vast improvement in linearity over previous network formulation method


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