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Lecture 12

Lecture 12. Latches Section 5.1-5.3, 9.1-9.2. Block Diagram of Sequential Circuit. g ates. New output is dependent on the inputs and the preceding values of outputs. Characteristic: the output node is intentionally connected back to inputs. Sequential Circuits.

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Lecture 12

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  1. Lecture 12 Latches Section 5.1-5.3, 9.1-9.2

  2. Block Diagram of Sequential Circuit gates New output is dependent on the inputs and the preceding values of outputs. Characteristic: the output node is intentionally connected back to inputs.

  3. Sequential Circuits • Two types of sequential circuits • Synchronous: circuits whose behavior can be defined from its signals at discrete instants of time. Clocks are to achieve synchronization. • Asynchronous circuits depend on input signals and the order in which the inputs change. (No clock pulses are used!)

  4. Block Diagram of Sequential Circuit Sychronous circuits: Used clocked flip-flops Asychronous circuits: Use unclocked flip-flops or time delay elements

  5. Applications of Asynchronous Circuits • Asynchronous circuits are important where the digital system must respond quickly without having to wait for a clock pulse • Useful in small independent circuits that require only a few components—where it may not be practical to go to the expense of providing a circuit for generating clock pulses!

  6. A Generic Asynchronous Circuit Yn is equal to yn only in the steady state! Combinational circuit produces propagation delay (2n-10ns) The delay element produced additional 1 ns delay per foot.

  7. Asynchronous Sequential Circuit Y1=xy1+x’y2 Y2=xy’1+x’y2

  8. Maps and Transition Table stable states: y1y2=Y1Y2

  9. Toggle x X= 0→1→0→1

  10. Latches • Latches are level sensitive. • Latches propagate values from input to output continuously. • S sets Q =1; R sets Q=0 • Active low inputs are enabled by 0s. • Active high inputs are enabled by 1s.

  11. SR Latch with NOR Gates Active High inputs tPDSQ=2 NOR gate delays. tPDRQ_=1 NOR gate delay SR are trigger pulses which can return to zero once Q is set. Forbidden State

  12. Typical Mode of Operation R must go back to 0 in order to avoid S=R=1. Q and Q’ do not change states when R goes back to 0. S must go back to 0 in order to avoid S=R=1. Q and Q’ do not change states when S goes back to 0. Both inputs of the latch remain at 0 unless the state has to be changed. When both S and R are equal to 0, the latch can be in either the set or the reset, depending on which input was most recently a 1.

  13. SR Latch with NAND Gates S must go back to 1 in order to avoid S=R=0. Q and Q’ do not change states when S goes back to 1. R must go back to 1 in order to avoid S=R=0. Q and Q’ do not change states when R goes back to 1. Both inputs of the latch remain at 1 unless the state has to be changed. When both S and R are equal to 1, the latch can be in either the set or the reset, depending on which input was most recently a 1.

  14. Comparison (activated with a 1) (activated with a 0)

  15. SR Latch with NAND Gates Active low inputs

  16. SR latch with Control Line (En=0) 1 0 1 1. En=0, Q and Q’ will not be changed!

  17. SR latch with Control Line (En=1) S’ 1 R’ En=1, Q and Q’ will be affected by S and R. We now have active-high enabled circuit!

  18. D Latch

  19. D Latch (En=0) 1 0 1

  20. D Latch (En=1) D’ 1 D Q follows D as long as En is asserted (En=1). Data is temporary stored when En is 0.

  21. D-latch Operation

  22. D-Latch (CK=0) D 0 0 0 DB

  23. D-Latch (CK=1) D D DB 1 D DB DB

  24. Analyze D Latch Using Boolean Algebra

  25. Transistor Level (Optional)Implementation of D-Latch

  26. Clock Generation Increment clkcdiv at The rising edge of mclk 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Clkdiv[2] toggles every 4 cycles Clkdiv[1] toggles every 2 cycles. Single pass behavior Cyclic behavior Non-blocking statements

  27. Initial keyword • Single-pass behavior • An initial behavior statement executes just once. • Initial statement executes at the start of simulation and expires after all of its statements have completed execution. • An initial statement is also a procedural statement

  28. always • always is a procedural assignment • The variables in the left hand side of procedural statement must be of the reg data type. • Clkdiv can not be a wire because clk is not updated until always sees positive edge of mclk. Therefore, clkc can not be a wire type.

  29. Continuous versus Procedural Statement Continuous statement: Clk_out is updated whenever Clkcdiv[2] changes. clk_out is a wire! Procedural statement Clkdiv is only incremented when a posedge of mclk is detected. clkdivis a reg!

  30. Blocking versus Nonblocking Statements • There are two kinds of procedural assignments: • Blocking statements • Use (=) as the assignment operator • Blocking statements are executed sequentially in the order they are listed. • Used to model behavior that are level sensitive (i.e. in combinational logic) • Nonblocking statements • Use (<=) as the assignment operator • Nonblocking statements are executed concurrently. • Used to model synchronous/concurrent behavior.

  31. Blocking Statements • B=A (transfers A to B) • C=B+1 (increments B and writes the value to C)

  32. Nonblocking Statements • B<=A • C<=B+1 • The value of A is kept in one storage location • The value of B+1 is stored in another storage location • After all the expressions in the block are evaluated and stored, the assignment to the targets on the left-hand side is made. • C will contain the original value of B, plus 1. This is the value of B before A is written into B.

  33. Top Level Verilog of clk_gen

  34. Generate a Test Vector Load test vector at t=0 Set dout equal to testvector[vectornum] at the rising edge of a dclk

  35. bit_str.txt Generate a bit file with rand() fundtion

  36. tvector simulation

  37. Verilog Model of d latch

  38. Test Bench

  39. Use a Digital Oscilloscope • Generate a binary vector in matlab • Load the binary vector onto the function generator

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