Dag aware aig rewriting a fresh look at technology independent combinational logic synthesis
This presentation is the property of its rightful owner.
Sponsored Links
1 / 17

DAG-Aware AIG Rewriting A Fresh Look at Technology-Independent Combinational Logic Synthesis PowerPoint PPT Presentation


  • 104 Views
  • Uploaded on
  • Presentation posted in: General

DAG-Aware AIG Rewriting A Fresh Look at Technology-Independent Combinational Logic Synthesis. Alan Mishchenko Satrajit Chatterjee Robert Brayton UC Berkeley. Overview. Motivation Previous work Example Experiments Conclusions. Motivation for Improved Synthesis.

Download Presentation

DAG-Aware AIG Rewriting A Fresh Look at Technology-Independent Combinational Logic Synthesis

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Dag aware aig rewriting a fresh look at technology independent combinational logic synthesis

DAG-Aware AIG Rewriting A Fresh Look at Technology-Independent Combinational Logic Synthesis

Alan Mishchenko Satrajit Chatterjee Robert BraytonUC Berkeley


Overview

Overview

  • Motivation

  • Previous work

  • Example

  • Experiments

  • Conclusions


Motivation for improved synthesis

Motivation for Improved Synthesis

  • Traditional combinational tech-independent synthesis

    • suboptimal

    • complicated

    • hard to implement

    • slow

  • We propose to replace it with synthesis that is

    • suboptimal, but

    • simple

    • easier to implement

    • fast


Previous work

Previous Work

  • Per Bjesse and Arne Boralv, "DAG-aware circuit compression for formal verification",ICCAD 2004

    • Pre-compute all two-level subgraphs

      • group them into equivalence classes by functionality

    • For each node in the topological order

      • Rewrite the subgraph rooted at a node, as long as area (the number of nodes) does not increase

        • Account for logic sharing (DAG-aware)

      • (Optional) Iterate until no improvement


Illustration

Subgraph 2

Subgraph 1

Subgraph 3

A

A

a

a

b

c

b

a

c

a

a

c

a

b

b

c

b

c

a

Subgraph 2

Subgraph 1

B

B

a

c

b

a

c

a

b

a

c

a

b

Subgraph 2

Subgraph 1

Illustration

  • Pre-computing subgraphs

    • Consider function f = abc

  • Rewriting subgraphs

Rewriting node A

Rewriting node B

In both cases 1 node is saved


Proposed approach

Proposed Approach

  • First, we introduce two concepts

    • NPN-classes of Boolean functions

    • k-feasible cuts in the network


Npn classes of boolean functions

  • Example 1:

    F = ab + c

    G = ac + b

= a + bc

NPN-Classes of Boolean Functions

  • Definition. Two functions belong to the same NPN-class (are NPN-equivalent) if one of them can be derived from the other by permuting inputs, complementing inputs, and complementing the output

  • Example 3:

    F = ab + c

    H = a(b+c)

  • Example 2:

    F = ab + c

    F = ab

NPN-equivalent

Not NPN-equivalent

NPN-equivalent


K feasible cuts

n

p

k

s

a

b

c

PIs: a, b, c

k-Feasible Cuts

  • Definition. A set of nodes C is a k-feasible cut for a node n if (1) all the paths from the primary inputs (PIs) to node n pass through at least one node in C,(2) the number of nodes in C does not exceed k

  • 3-feasible cuts of n:

    C1 = { p, k }

    C2 = { a, b, s }

  • Not 3-feasible cuts of n:

    C3 = { p, b, c }

    C4 = { a, b, s, c }


Proposed approach1

Proposed Approach

  • Pre-compute AIGs with non-redundant structure for all NPN-classes of 4-variable functions

    • The total number (222)

    • Appear in benchmark circuits (~100)

    • Account for 99% of area implement in rewriting (~40)

  • For each node in the topological order

    • Compute all 4-input cuts (on average, 6 cuts per node)

    • Match each cut into its NPN class (a hash table lookup)

    • Try all structural implementations of the class, choose the best

    • If the area (and delay!) does not increase, accept the change


Example of rewriting s27 blif

Example of Rewriting (s27.blif)

3 levels

3 levels

4 nodes

3 nodes

The number of AIG nodes is reduced. The number of AIG levels is the same.


Experimental results

Experimental Results

  • Cost functions for technology-independent synthesis

    • The number of factored form literals (the previous work)

    • The number of AIG nodes and levels (the proposed work)

  • These cost functions are “apples” and “oranges”

  • For fairness, the comparison is done after mapping

    • Using MCNC benchmarks (vs. SIS and MVSIS)

    • Using IWLS 2005 benchmarks (vs. MVSIS)

  • ABC mapper for standard cells and FPGAs is used


Experimental setup

Experimental Setup

  • ABC script “resyn2”

    • “b; rw; rf; b; rw; rwz; b; rfz; rwz; b”

      (performs 10 rewriting passes over the network)

      • b (balance) tries to reduce delay without increasing area

      • rw/rf (rewrite/refactor) tries to reduce area without increasing delay

      • rwz/rfz the same as above, but allow for zero-cost replacements

  • MVSIS “mvsis.rugged”

  • SIS “script.delay” and “script.rugged + speed_up”

  • Runtimes are measured on 1.6GHz CPU


Experimental results mcnc

Experimental Results (MCNC)


Iwls 2005 benchmark statistics

IWLS 2005: Benchmark statistics


Iwls 2005 standard cell mapping

IWLS 2005: Standard-Cell Mapping


Iwls 2005 fpga mapping k 5

IWLS 2005: FPGA Mapping (k=5)


Conclusions

Conclusions

  • Introduced ABC

  • Presented DAG-aware AIG rewriting

  • Showed promising experimental results

  • Future work

    • AIG rewriting with larger cut size

    • Sequential AIG rewriting


  • Login