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Performed by: Gidi Getter , Shir Borenstein Supervised by: Ina Rivkin Mid-Term Presentation

Technion - Israel institute of technology department of Electrical Engineering. הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל. High speed digital systems laboratory. המעבדה למערכות ספרתיות מהירות. Space Wire Core for LEON3 System.

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Performed by: Gidi Getter , Shir Borenstein Supervised by: Ina Rivkin Mid-Term Presentation

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  1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Space Wire Core for LEON3 System Performed by: Gidi Getter, Shir BorensteinSupervised by: Ina Rivkin Mid-Term Presentation 14/01/2007

  2. Design a Space Wire core for LEON3 system. Load system to GR-RASTA board and test point to point SW connection via Space Wire Bridge. Project Definition

  3. Space Wire Link LVDS LEON3 System JTAG RS232 LEON3 Processor JTAG Dbg Link SERIAL Dbg Link AMBA AHB Bus AHBController MemoryController RAM SRAM, DRAM etc.

  4. SpaceWire Protocol has different type of characters / codes: Packet Level: NChar, EOP, EEP Exchange Level: FCT, Null TimeCode SpaceWire Protocol - Reminder

  5. Space Wire Core – Top Level clk data_out data_out 9 bit 9 bit Data TransmitFIFO read_en write_en Transmitter Strobe tick_in + time_in +control_flags_in read_clk write_clk tr_rst AMBABus sendFCTs/NChars/Nulls/Timecodes clk AMBA Controller Controller Space Wire Link LEON 3 sendFCT_req+ack gotFCT_req+ack gotFCT/NChar/NullEOP/EEP/TimeCode rst Rx/Credit Error rec_rst Data data_in data_in ReceiveFIFO tick_out + time_out +control_flags_out Receiver 9 bit 8 bit Strobe write_en read_en write_clk read_clk clk

  6. SW Core has 3 clock domains: System clock, Receiver Clock, Transmitter clock. Data transfer between Transmitter or Receiver and host system is done by packet level. Exchange level (FCT, Null etc) is not forward to FIFO or Bus controller. Packet transfer are synchronized via double clock FIFOs. Control signals between Transmitter and Receiver are synchronized using a 4-phase hand shake protocol. In the controller we use another method which logs whether an event occurred on the input. Synchronize Clock Domains

  7. Space Wire Core – Top Level clk data_out data_out 9 bit 9 bit Data TransmitFIFO read_en write_en Transmitter Strobe tick_in + time_in +control_flags_in read_clk write_clk tr_rst AMBABus sendFCTs/NChars/Nulls/Timecodes clk AMBA Controller Controller Space Wire Link LEON 3 sendFCT_req+ack gotFCT_req+ack gotFCT/NChar/NullEOP/EEP/TimeCode rst Rx/Credit Error rec_rst Data data_in data_in ReceiveFIFO tick_out + time_out +control_flags_out Receiver 9 bit 8 bit Strobe write_en read_en write_clk read_clk clk

  8. clk CreditError RxError Link_Disabled rst ctrl_rst gotFCT gotFCT_ctrl rec_rst gotNull gotNull_ctrl tr_rst controllerstate-machine controllersynchronizer gotTimeCode gotTimeCode_ctrl sendNulls gotNChar gotNChar_ctrl sendFCTs gotEOP gotEOP_ctrl sendNChars gotEEP gotEEP_ctrl sendTimeCodes restart timeout_6_4 ctrl_rst ctrl_rst ctrl_rst timeout_12_8 ‘1’ D Q D Q D Q gotFCT clk timer rst clk Space Wire Core – Controller

  9. Space Wire Core – Top Level clk data_out data_out 9 bit 9 bit Data TransmitFIFO read_en write_en Transmitter Strobe tick_in + time_in +control_flags_in read_clk write_clk tr_rst AMBABus sendFCTs/NChars/Nulls/Timecodes clk AMBA Controller Controller Space Wire Link LEON 3 sendFCT_req+ack gotFCT_req+ack gotFCT/NChar/NullEOP/EEP/TimeCode rst Rx/Credit Error rec_rst Data data_in data_in ReceiveFIFO tick_out + time_out +control_flags_out Receiver 9 bit 8 bit Strobe write_en read_en write_clk read_clk clk

  10. sentFCT_ack transmitter -receiverFCT exchange clk sentFCT_req gotFCT_req tick tr_clk gotFCT_ack tr_clk tr_rst tick_tr gotFCT FIFO_empty time_code_tr sendNull tick_in tick_in_tr data path -characterserialization inputsync unit transmittercontrolunit sendTimeCode D_out time_in has_places_tr sendNChar S_out ctrl_flags_in tr_clk sendFCT tr_rst has_places rd_en last_cycle tr_rst tr_clk tr_clk tr_rst FIFO_data_out sendTimeCodes sendNChars sendFCTs sendNulls clk DCM tr_rst Space Wire Core – Transmitter

  11. Four Phase Protocol Data Transmitter Strobe req gotFCT req gotFCT ack ack Data Receiver Strobe

  12. Space Wire Core – Top Level clk data_out data_out 9 bit 9 bit Data TransmitFIFO read_en write_en Transmitter Strobe tick_in + time_in +control_flags_in read_clk write_clk tr_rst AMBABus sendFCTs/NChars/Nulls/Timecodes clk AMBA Controller Controller Space Wire Link LEON 3 sendFCT_req+ack gotFCT_req+ack gotFCT/NChar/NullEOP/EEP/TimeCode rst Rx/Credit Error rec_rst Data data_in data_in ReceiveFIFO tick_out + time_out +control_flags_out Receiver 9 bit 8 bit Strobe write_en read_en write_clk read_clk clk

  13. New data arrives at both clock rise and clock fall. Use 2 Flip-Flops to sample data: One at clock rise and one at clock fall. At clock rise a vector of 2 bits is forwarded by the sampler, allowing the receiver to run on the external clock. Data Sampling Clk D S Data

  14. data_in D_in write_en rec_clk S_in charactersequence& errordetector gotTimeCode gotFCT_ack sentFCT_req gotEOP rec_rst rec_clk clk gotEEP rec_clk D receiver -transmitterFCT exchange 0 1 0 0 10 00 gotNChar rec_rst gotFCT D_in gotNull1 parallel2-bit rec_clk d2 gotNull enable rec_rst gotFCT_req sentFCT_ack CreditError gotNull2 first NULLsequencedetector rec_clk clk90 rec_rst parity/escapeerror RxError rec_clk locked_out DCM timeout rec_rst receiverstate-machine& timer rec_clk clk rec_rst Space Wire Core – Receiver

  15. Space Wire Core – Top Level clk data_out data_out 9 bit 9 bit Data TransmitFIFO read_en write_en Transmitter Strobe tick_in + time_in +control_flags_in read_clk write_clk tr_rst AMBABus sendFCTs/NChars/Nulls/Timecodes clk AMBA Controller Controller Space Wire Link LEON 3 sendFCT_req+ack gotFCT_req+ack gotFCT/NChar/NullEOP/EEP/TimeCode rst Rx/Credit Error rec_rst Data data_in data_in ReceiveFIFO tick_out + time_out +control_flags_out Receiver 9 bit 8 bit Strobe write_en read_en write_clk read_clk clk

  16. Leon3 reads data one packet at a time. All NChars are forwarded from FIFO1 to FIFO2 until EOP/EEP is detected. No further data is written into FIFO2 until is the packet was read by Leon3 and FIFO2 is empty again. Receiver FIFO Got_EOP Got_EEP 9 8 data_in ReceiveFIFO1 ReceiveFIFO2 data_out Data Data FIFO Controller wr_en read_en wr_clk rd_en wr_en read_clk

  17. Space Wire Core – Top Level clk data_out data_out 9 bit 9 bit Data TransmitFIFO read_en write_en Transmitter Strobe tick_in + time_in +control_flags_in read_clk write_clk tr_rst AMBABus sendFCTs/NChars/Nulls/Timecodes clk AMBA Controller Controller Space Wire Link LEON 3 sendFCT_req+ack gotFCT_req+ack gotFCT/NChar/NullEOP/EEP/TimeCode rst Rx/Credit Error rec_rst Data data_out data_in ReceiveFIFO tick_out + time_out +control_flags_out Receiver 9 bit 8 bit Strobe write_en read_en write_clk read_clk clk

  18. AHB Operation

  19. AHB Address Decoding

  20. Handles all requests from processor. Reads and writes data from FIFOs to transfer between core and processor. Add bit for data/EOP. Updates Status Register. Informs available room in receive FIFO for FCT handling by transmitter. AMBA AHB Controller 9 Data clk wr_en State Machine 8 Data reset rd_en Tick_out AHB_slave_in Time_out StatusRegister AHB_slave_out Tick_in Time_in

  21. Send Data from Leon3 via SW Leon3 reads status register Not enough room for all data Enough room for all data writes all the data to SW core Write until FIFO is full Data it is written into transmitter FIFO. 9th bit for Data/EOP is added.

  22. Receive Data via SW Leon3 reads status register End of Packet received More than 28 bytes on FIFO Read 28 bytes Read all the data from FIFO When packet is transferred to Leon3, data can move from FIFO1 to FIFO2 on the receiver side

  23. Complete implementation of the Core in VHDL – 1 week Perform logic simulation of the design with loopback & debug – 2 weeks Synthesize and load design to GR-RASTA board – 1 week Simulate the design and debug using ChipScope – 2 weeks Simulate system with SW bridge, performance analysis – 1-2 weeks Development Steps

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