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VHDL ORGANIZATION AND ARCHITECTURE

VHDL ORGANIZATION AND ARCHITECTURE. FREDY AGUAS GINETH BUSTOS. VHDL.

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VHDL ORGANIZATION AND ARCHITECTURE

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  1. VHDL ORGANIZATION AND ARCHITECTURE FREDY AGUAS GINETH BUSTOS

  2. VHDL VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.

  3. There are five types of design units in VHDL • entitydeclaration • Architecture • Configuration • packagedeclaration • packagebody

  4. Entity A VHDL entity specifies the name of the entity, its ports and all information related to it. Entity led is Port (A,B,C: in STD_LOGIC; F: out STD_LOGIC); End led;

  5. Entity: Port I / O Port: input or output. All ports must have: name, data type and mode

  6. DATA TYPE IN VHDL

  7. Declaration of entities through libraries and packages • Librerías IEEE y WORK. • IEEE: paquete std_logic_1164 • WORK: numeric_std, std_arith. • Paquete: containspresetalgorithms

  8. Architecture In general, programming styles used in architectures el desingknow classified as • Functional (Behavioral). Defines a process described sequentially. • Data Flow (Dataflow). Includes structure and behavior • Structural (Structural). Defining interconnections and components.

  9. Functional (Behavioral) architecture ARQ1 of COMPARA is begin process(A,B) begin if(A=B) then C <= ‛1’ after 1 ns; else C <= ‛0’ after 2 ns; endif; endprocess; EndARQ1

  10. Data Flow (Dataflow) Entity XR2 is generic (m: time := 1.0 ns); -- Tiempo de retardo port (X,Y: in bit; Z: out bit); End XR2; architecture DATAFLOW of XR2 is begin Z <= X xor Y after m; --Retardo genérico end DATAFLOW;

  11. Structural Entity COMPARA is --Entity port (A,B: in bit; C: out bit); End COMPARA; architecture STRUCT of COMPARA is SIGNAL I: bit; --Declaration of components component XR2 port (x,y: in bit; z: out bit); end component; component INV port (x: in bit; z: out bit); end component; begin U0: XR2 portmap (A,B,I); --Components U1: INV portmap (I,C) --utilizadosendSTRUCT;

  12. Architecture It is the structure that defines the operation of an entity. ARCHITECTURE dataflow of mux IS SIGNAL select : INTEGER; BEGIN select <= 0 WHEN s0 = „0‟ AND s1 = `0´ELSE 1 WHEN s0 = „1‟ AND s1 = `0´ELSE 2 WHEN s0 = „0‟ AND s1 = `1´ELSE 3 ; z <= a AFTER 0.5 NS WHEN select = 0 ELSE b AFTER 0.5 NS WHEN select = 1 ELSE c AFTER 0.5 NS WHEN select = 2 ELSE d AFTER 0.5 NS; END dataflow;

  13. GRACIAS

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