the d silicon track trigger
Download
Skip this Video
Download Presentation
The D Ø Silicon Track Trigger

Loading in 2 Seconds...

play fullscreen
1 / 26

The D Ø Silicon Track Trigger - PowerPoint PPT Presentation


  • 65 Views
  • Uploaded on

The D Ø Silicon Track Trigger. Wendy Taylor SUNY Stony Brook D Ø Oklahoma Workshop July 8, 2002. Introduction Design Status Schedule. Physics Motivation. Increase inclusive production yield six-fold with low enough threshold to see signal

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' The D Ø Silicon Track Trigger' - sybill-jordan


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
the d silicon track trigger

The DØ Silicon Track Trigger

Wendy Taylor

SUNY Stony Brook

DØ Oklahoma Workshop

July 8, 2002

  • Introduction
  • Design
  • Status
  • Schedule
physics motivation
Physics Motivation
  • Increase inclusive production yield six-fold with low enough threshold to see signal
    • Control sample for b-jet energy calibration, mass resolution, b trigger and tagging efficiencies
  • Top quark physics
    • Factor of 2 improvement in top mass resolution due to improved jet energy scale calibration
  • Heavy resonances for Higgs searches
    • Double trigger efficiency for by rejecting QCD gluons and light-quark jets
  • -quark physics
    • Lower pT threshold on single lepton and dilepton triggers ( , Bs mixing, etc.)
    • Increase yield by 50% (CP violation)

Wendy Taylor

d trigger system

Detector

L1 Trigger

L2 Trigger

7 MHz

5-10 kHz

1000 Hz

L1CAL

L2Cal

CAL

FPS

CPS

L2PS

L1

CTT

Global

L2

L2CFT

CFT

L2STT

SMT

L2

Muon

L1

Muon

Muon

L2FW:Combined

objects (e, m, j)

L1FPD

FPD

L1FW: towers, tracks, correlations

DØ Trigger System

Wendy Taylor

stt overview
STT Overview

1-mm road

CFT A layer

CFT H layer

SMT barrels

Wendy Taylor

stt design expectations
STT Design Expectations
  • STT latency of 50 s
  • Impact parameter resolution of 35 m
    • 30-m beam spot
    • 15-m impact parameter resolution
  • Momentum resolution dependent on pT but a factor of 2 improvement over L1CTT predicted

Wendy Taylor

contributing institutions
Contributing Institutions
  • Boston University
    • U. Heintz, M. Narain, L. Sonnenschein (PD), J. Wittlin (PD), K. Black (GS), S. Fatakia (GS), A. Zabi (GS), E. Hazen (Eng), S. Wu (Eng)
  • Columbia University
    • H. Evans, G. Steinbrück (PD), T. Bose (GS), A. Qi (Eng)
  • Florida State University
    • H. Wahl, H. Prosper, S. Linn, T. Adams, B. Lee (PD), S. Tentindo Repond (PD), S. Singupta (GS), J. Lazoflores (GS)
  • SUNY Stony Brook
    • J. Hobbs, W. Taylor (PD), H. Dong (GS), C. Pancake (Eng), B. Smart (Eng), J. Wu (Eng)

Wendy Taylor

stt design
STT Design

L2 Global

L1CTT

L2 Global

CPU

spare

spare

SBC

spare

spare

terminator

TFC

STC

STC

STC

STC

STC

FRC

STC

STC

STC

STC

TFC

spare

terminator

6 Identical Crates with

1 Fiber Road Card

9 Silicon Trigger Cards

2 Track Fit Cards

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

Sector 1

Sector 2

Wendy Taylor

motherboard design
Motherboard Design
  • Boston University
  • 9Ux400 mm VME64x-compatible
  • 3 33-MHz PCI busses for on-board communications
  • Data communicated between cards via point-to-point links (LVDS) (LTB and LRB cards)
  • Control signals sent over backplane using dedicated lines
  • VME bus used for Level 3readout and initialization/monitoring

Wendy Taylor

fiber road card frc design
Fiber Road Card (FRC) Design
  • Columbia University
  • Receives tracks from the Level 1 CTT trigger (via a VTM) and transmits this information to the other cards
  • Communicates with the trigger framework via an SCL receiver card on motherboard and broadcasts any control signals to the other cards
  • Handles buffering and readout to Level 3 via Buffer Controller (BC) daughter cards on each motherboard
  • FRC logic implemented in 6 FPGAs

Wendy Taylor

fiber road card design
Fiber Road Card Design

FRC

Link Transmitter Board

Link Receiver Board

Buffer

controller

Wendy Taylor

silicon trigger card stc design
Silicon Trigger Card (STC) Design
  • Boston University
  • Performs SMT clustering and cluster-road matching
    • Neighbouring SMT hits (axial and stereo) are clustered using an FPGA programmed in VHDL
      • Use 5 strips for centroid
    • Each STC processes 8 HDI inputs simultaneously
    • Axial clusters are matched to ±1mm-wide roads around each CFT track via precomputed LUT
    • Bad strips are masked (LUT)
    • Pedestals/gains are calibrated (chip-by-chip LUTs)

Wendy Taylor

silicon trigger card design
Silicon Trigger Card Design

Road

LUT

FPGA

Wendy Taylor

track fit card tfc design
Track Fit Card (TFC) Design
  • SUNY Stony Brook
  • Performs final SMT cluster filtering and track fitting
    • Eight DSPs each receive 2 CFT hits and axialSMT clusters in road defined by CFT track
    • Lookup table used to convert hardware to physical coordinates
    • C program on DSP selects clusters closest to road center at each of 4 layers and performs a linearized track fitusing precomputed matrix elements stored in on-board LUT
    • Allows tracks with hits on only 3 SMT layers for improved efficiency
  • Output to L2CTT via Hotlink cards

Wendy Taylor

track fit card design
Track Fit Card Design

Matrix LUT

Coordinate Conversion LUT

Hotlink Card

DSP

Wendy Taylor

initialization and monitoring
Initialization and Monitoring
  • Florida State University and Boston University
  • PowerPC crate controller
    • Initializes STT cards at power-up
    • Downloads lookup tables and DSP code to STT cards
    • Existing test-mode uses Python; conversion to C for final system ongoing
  • EPICS STT board support package
    • Downloads via COMICS trigger initialization parameters
    • Gathers information from cards for monitoring purposes
    • Under development; expect completion by late July

Wendy Taylor

l2sttcttworker
L2STTCTTWorker
  • Boston University
  • Online package that receives L2 STT output information
    • Formats and orders it appropriately
      • Stage 1: Ordered by impact parameter significance
      • Stage 2: Ordered by pT
    • Transmits it to L2 Global for final L2 decision
  • Code under development
  • Expect it to be operational by late August

Wendy Taylor

stt trigger simulator
STT Trigger Simulator
  • Florida State University and SUNY Stony Brook
  • Stand-alone package is available (tsim_l2stt)
  • Exact DSP fitting code used in tsim_l2stt
  • Some ongoing development to improve the emulation of the hardware/firmware
  • Will be integrated into d0trigsim by end of July
  • Has been instrumental in developing the fitting algorithm

Wendy Taylor

impact parameter resolution
Impact Parameter Resolution

50 GeV/c muons,

No beam spot

 = 20 m

Wendy Taylor

hardware status
Hardware Status
  • Prototypes of all boards in hand
  • Hardware design complete
  • Production status (460 boards)
    • 35% complete
    • 50% in progress
    • 15% evaluating preproduction samples
  • Firmware debugging in progress
  • Integration tests ongoing

Wendy Taylor

integration tests
Integration Tests
  • LTB  LRB : 6x1015 bits transferred without errors
  • Hotlink  MBT : 3x1010 bits transferred without errors
  • Used fake data sender (tracks to FRC and hits to STC) to verify FRC  STC, FRC  TFC and STC  TFC transfers
  • FRC  BC and TFC  BC communications tested, STC  BC ongoing
  • Continue FRC  STC  TFC test with fake data sender
  • Test FRC  STC  TFC chain with fakeAFE CTT track in time with real SMT data

Wendy Taylor

schedule
Schedule
  • now – August: Integration
    • communication with L1CTT, SCL, SBC
    • rack configuration complete
    • board production continuing
  • September: complete 30° sector
    • parasitic operation
    • full track reconstruction
    • output to L3 and private DAQ for L2
  • October: production complete
    • installation during shutdown
  • November: commissioning of full STT

Wendy Taylor

run 2b silicon track trigger
Run 2B Silicon Track Trigger
  • Run 2B SMT detector has 6 layers
  • Run 2B STT can process hit information from 5 layers
  • Achieved by doubling the number of Track Fit Cards in each crate

Wendy Taylor

hardware status backup
Hardware Status (backup)
  • Prototypes of all boards in hand
  • Hardware design complete
  • Integration/Firmware debugging in progress
  • Production Status (460 boards)
    • 35% complete
    • 50% in progress
  • 15 (72) Motherboards working, expect remaining by mid-September
  • 30 link receivers/transmitters each assembled. Remaining expected by late August
  • 30 Hotlink transmitters almost fully assembled

Wendy Taylor

logic card status backup
Logic Card Status (backup)
  • 10 FRCs assembled, 9 working, 6 req’d + spares
  • 91 Buffer Controllers assembled, 73 working, 72 req’d + spares
  • 7 STCs assembled, 3 working, 54 req’d + spares
    • Once BGA mount problems are solved (select capable vendor) will go into production
  • 11 TFCs assembled, 7 working, 12 req’d + spares
    • 3 in rework, 4 new boards sent to new vendor

Wendy Taylor

efficiency vs rejection backup
Efficiency vs Rejection (backup)

Signal: ZH sample

Background: QCD, pT>10, 20, 40, 80, 160 GeV/c; merged

No cuts defines efficiency = rejection = 1

Cut on largest IP significance

in event (good tracks)

Wendy Taylor

ad