Data Controller Board Engineering Peer Review Dorothy Gordon University of California - Berkeley

1. Data Controller BoardEngineering Peer ReviewDorothy Gordon University of California - Berkeley

2. DCB Overview • Data Controller Board • Requirements • Block Diagram • Simulation Schematic and FPGA Subsystems • DMA & Interfaces • DCB ETUs: Test Results and Design Status • Next

3. DCB Requirements • IDPU System Processor • Interfaces to Spacecraft and Themis Instrument Subsystems • Manages communication to/from BAU and Instrument CDIs • Solid State Recorder (SSR) • Provides 256Mbytes of SDRAM with ECC option • Instrument Mode Setup and Data Management • CDI Interfaces • Timekeeping • Spin system timing (SpinClock and SpinSynch Generation) • Spacecraft Clock distribution and synchronization • Telemetry Buffer management • Housekeeping • ADC and Analog Mux

4. DCB - System Block Diagram

5. DCB-FPGA Instrument Command Interfaces Instrument Data Interfaces DCB-FPGA SSR Processor Bus BAU-STLM BAU-SCMD Simulation Schematic

6. FPGA Subsystems • CPU Interface - Bus Control & Paging • Instrument Data Interfaces - FGE, ETC & DFB (and DMA subsystems) • Command Interfaces - FGE, DAP, ETC, PCB & EFI (BEB, DFB) • Timekeeper - Timer Interrupt; Subseconds Clock; Watchdog Timer; Spin Timing Subsystem • BAU UART - “slow” telemetry and command I/Fs (and DMA subsystems) • BAU 2MHz Data Link - “high-speed” telemetry link, packet generation/management (and DMA subsystems) • SRAM Controller - clients are CPU, DFB, ETC, HST, FGML, SCMD, STLM & GDMA • SDRAM Controller - clients are DFB, ETC, HST, FGMH, FGML, CPU, GDMA & Scrubber

7. Instrument DMA • Instruments allocated 4Kbyte buffers - typically directed into the SSR (certain channels can write into SRAM or registers ) • DCB Control Logic implements double-buffering for all Instrument DMA. Buffer swapping initiated with programmable timing “ticks” - synchronized to either SPINSYNCH or the 1HZ Clock • DFB - allocated 17 channels, Data-ID selects channel (15 SSR/SRAM and 2 SRAM only) • FGE - two independent telemetry interfaces: FGE-L (SDRAM or SRAM) and FGE-H (SDRAM only; data also written to register I/F). Full vectors + 8 bits of status available via register I/F. Pre-scaled vectors written into memory. • ETC - allocated 13 SSR/SRAM channels and 1 register based I/F, Data-ID selects channel

8. Spacecraft DMA • UART DMA • Command UART - allocated 1024 byte single-buffered DMA Page - SRAM based • Slow Telemetry UART - allocated 256 byte single buffered DMA Page - SRAM based • “High-Speed” Data I/F • Control Logic performs framing -- Flight Software queues packets (up to 16Kbyte buffers) - Double Buffered - SRAM or SDRAM based

9. Interface Test/Verification • All DCB interfaces have been exercised/verified:

10. DCB Board Layout

11. DCB Board

12. DCB Test Setup

13. DCB Power • Parts Stress Analysis • Stress analysis completed for DCB Parts. • Complies with GSFC PPL-21 derating guidelines. • Measured Power • Current Drain: • Digital: 50mA @ 2.5V; 180mA @5V (SSR off); 230mA @ 5V (SSR on) • Analog: 15mA @ +5V; 20mA @ -5V; 1.5mA @10V; 0.75mA @ -10V • Estimated Power Drain, Flight DCB: • 1.5W (flight FPGA requires 3X current from the 2.5V supply)

14. DCB Design Status • DCB ETU Initial Design complete • Three DCB-ETU PCBs have been built and tested • Design Environment (monitor - debug code) established • DCB FPGA • Undergoing incremental changes as a result of testing & integration with flight software • Issues • Actel 54SX family problems

15. DCB - Next • DCB Testing: • Generate more extensive and marathon diagnostics; perform intensive tests using SSL supplied GSE • DCB Integration: • DCB-ETUs with Instrument Subsystems - verify CDI Interfaces • Integrate with BAU - verify S/C Interfaces • FPGA Modifications: • Next major revision adds ECC Subsystem & General Purpose DMA Controller