1 / 20

Lecture 10 Chap 12: Special Structure

Lecture 10 Chap 12: Special Structure. Instructors: Fu-Chiung Cheng ( 鄭福炯 ) Associate Professor Computer Science & Engineering Tatung University. Outline. Tristates Finite state machines. Tristates. If en = 1 then q=d otherwise q is high impedance.

swain
Download Presentation

Lecture 10 Chap 12: Special Structure

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Lecture 10Chap 12: Special Structure Instructors: Fu-Chiung Cheng (鄭福炯) Associate Professor Computer Science & Engineering Tatung University

  2. Outline • Tristates • Finite state machines

  3. Tristates • If en = 1 then q=d otherwise q is high impedance. • High impedance ==> high resistance ==> cut off

  4. Tristate Driver process (d, en) begin if en = ‘1’ then q <= d; else q <= ‘Z’; end if; end process; Note that the pattern(template) is apparently containing a two-way multiplexer modeled by if statement.

  5. Tristate Driver • It is not possible to describe a regiser with a tristable • output as a single process. • The exact rules for writing tristate drivers will vary • between synthesizers. • Tristate template: • if statement with two branches: • A. one containing high-impedance assignment • B. the other containing any other combinational • logic. • Tristate drivers (bus) is simply a signal of a subtype, • (resolved subtype), which can model tristates. • Use std_logic only

  6. Tristates architecture behavior of tristate is begin process (d, en) begin if en = ‘1’ then q <= d; else q <= ‘Z’; end if; end process; end; library ieee; use ieee.std_logic_1164.all; entity tristate is port (d : in std_logic; en : in std_logic; q : inout std_logic); end;

  7. Tristate Bus • Tristate bus can be created by using any array of • std_logic, such as std_logic_vector, signed and • unsigned • The assignment of value ‘Z’ is changed into an array • of a string ‘Z’ values. • Q <= (others => ‘Z’); • Examples:

  8. Tristate Bus architecture behavior of tristate_vec is begin process (d, en) begin if en = ‘1’ then q <= d; else q <= “ZZZZZZZZ”; end if; end process; end; library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; entity tristate_vec is port (d : in signed(7 downto 0); en : in std_logic; q : inout signed(7 downto 0)); end;

  9. architecture behavior of tristate_mux is begin t0: process (en, sel,a) begin if en = ‘1’ and sel = ‘0’ then z <= a; else z <= (others => ‘Z’); end if; end process; t1: process (en, sel, b) begin if en = ‘1’ and sel = ‘1’ then z <= b; else z <= (others => ‘Z’); end if; end process; end; library ieee; use ieee.std_logic_1164.all; entity tristate_mux is port (a, b, sel, en: in std_logic; z:inout std_logic); end;

  10. library ieee; use ieee.std_logic_1164.all; entity tristate_mux is port (a, b, sel, en : in std_logic; z : inout std_logic); end; architecture behavior of tristate_mux is begin process (en, sel,a, b) begin if en = ‘1’ then --tristate driver if sel = ‘0’ then --multiplexer z <= a; else z <= b; end if; else z <= (others => ‘Z’); end if; end process; end;

  11. Finite State Machines • Finite State Machine(FSM): is a sequential circuit in • which the next state and the circuit outputs depend • on the current state and the inputs. • The most common FSM applications are in control • circuits. • FSM=CL block • + register block • Most synthesizers • have the capability • of performing • state optimization • on FSMs

  12. Finite State Machines • Finite state machine template varies slightly from one • synthesizer to another. • Key feature of the FSM template: • current state and next state are represented by an • enumeration type, with one value for each state. • State signal may need to be identified so that the • synthesizer knows how to apply state optimization. • Example: a FSM that detects a certain bit sequence on • one-bit-wide serial input.

  13. Sequence Detection Machine

  14. library ieee; use ieee.std_logic_1164.all; entity signature_detector is port (d, ck : in std_logic; found : out std_logic); end; architecture behavior of signature_detector is type state_type is (start, found1, found0, detect); attribute enum_encoding of state_type: type is “00 01 11 10”; signal current_state, next_state : state_type; begin process -- register block begin wait until ck’event and ck = ‘1’; current_state <= next_state; end process; process (current_state, d) begin case current_state is when start => found <= ‘0’; if d = ‘1’ then next_state <= found1; else next_state <= start; end if;

  15. when found1 => found <= ‘0’; if d = ‘0’ then next_state <= found0; else next_state <= found1; end if; when found0 => found <= ‘0’; if d = ‘1’ then next_state <= detect; else next_state <= start; end if; when detect => found <= ‘1’; if d = ‘1’ then next_state <= found1; else next_state <= found0; end if; end case; end process; end;

  16. library ieee; use ieee.std_logic_1164.all; entity signature_detector is port (d, ck : in std_logic; found : out std_logic); end; architecture behavior of signature_detector is type state_type is (start, found1, found0, detect); attribute enum_encoding of state_type : type is “00 01 11 10”; signal state : state_type; begin process -- register block begin wait until ck’event and ck = ‘1’; case state is when start => if d = ‘1’ then state <= found1; else state <= start; end if;

  17. when found1 => if d = ‘0’ then state <= found0; else state <= found1; end if; when found0 => if d = ‘1’ then state <= detect; else state <= start; end if; when detect => if d = ‘1’ then state <= found1; else state <= found0; end if; end case; end process; process (state) begin case state is when start => found <= ‘0’; when found1 => found <=‘0’; when found0 => found <=‘0’; when detect => found <=‘1’; end case; end process; end;

  18. process begin wait until ck’event and ck = ‘1’; if rst = ‘1’ then current_state <= start; else current_state <= next_state; end if; end process;

  19. library ieee; use ieee.std_logic_1164.all, ieee.numeric,_std.all; entity register_bank is generic (w, n: natural); port (d: in signed(w-1 downto 0); ck, write : in std_logic; addr : in unsigned (n-1 downto 0); q : out signed(w-1 downto 0)); end;

  20. architecture behavior of register_bank is signal addr_I : natural range 0 to 2**n-1; type store_type is array (0 to 2**n-1) of signed (w-1 downto 0); signal store : store_type; begin addr_I <= to_integer(addr); process begin wait until ck’event and ck = ‘1’; if write = ‘1’ then store(addr_I) <= d; end if; end process; q <= store(addr_I); end;

More Related