Determining the Optimal Process Technology for Performance-Constrained Circuits

1. Determining the Optimal Process Technology for Performance-Constrained Circuits Michael Boyer & Sudeep Ghosh ECE 563: Introduction to VLSI December 5th, 2006

2. Outline • Motivation • Methodology • Related work • Results • Conclusion

3. Performance Classes • Unconstrained • General-purpose microprocessors • Constrained • Digital signal processors • Many embedded devices • Relation to technology scaling

4. Methodology • Build circuit in multiple technologies • Vary supply voltage and measure: • Delay • Active power • Leakage power • Vary duty cycle and frequency and compute minimum power

5. Circuit

6. PTM Threshold Voltages

7. Total Power Calculation = activity factor T = circuit delay Ttarget = maximum delay = 1 / frequency

8. Related Work • 1995: Minimizing Power Consumption in Digital CMOS Circuits • Chandrakasan & Brodersen • 2005: An Ultra Low Power System Architecture for Sensor Network Applications • Hempstead, et al

19. Conclusion • 0.6um best choice for low duty cycle, low frequency operation • Problems: • PTMs • 1.6um

20. References • S. Borkar, “Design Challenges of Technology Scaling”, IEEE Micro, vol. 19, no. 4, pp. 23-29, 1999. • A. Chandrakasan and R. Brodersen, “Minimizing Power Consumption in Digital CMOS Circuits”, Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, 1995. • M. Hempstead, et al, “An Ultra Low Power System Architecture for Sensor Network Applications”, Proceedings of the 32nd International Symposium on Computer Architecture, 2005. • Y. Cao, et al, “New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Simulation”, CICC, pp. 201-204, 2000. • C. Hu, “BSIM Model for Circuit Design Using Advanced Technologies”, Symp. VLSI Circuits, pp. 5-6, 2001.