Determining the optimal process technology for performance constrained circuits
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Determining the Optimal Process Technology for Performance-Constrained Circuits. Michael Boyer & Sudeep Ghosh ECE 563: Introduction to VLSI December 5 th , 2006. Outline. Motivation Methodology Related work Results Conclusion. Performance Classes. Unconstrained

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Determining the Optimal Process Technology for Performance-Constrained Circuits

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Determining the optimal process technology for performance constrained circuits

Determining the Optimal Process Technology for Performance-Constrained Circuits

Michael Boyer & Sudeep Ghosh

ECE 563: Introduction to VLSI

December 5th, 2006


Outline

Outline

  • Motivation

  • Methodology

  • Related work

  • Results

  • Conclusion


Performance classes

Performance Classes

  • Unconstrained

    • General-purpose microprocessors

  • Constrained

    • Digital signal processors

    • Many embedded devices

  • Relation to technology scaling


Methodology

Methodology

  • Build circuit in multiple technologies

  • Vary supply voltage and measure:

    • Delay

    • Active power

    • Leakage power

  • Vary duty cycle and frequency and compute minimum power


Circuit

Circuit


Ptm threshold voltages

PTM Threshold Voltages


Total power calculation

Total Power Calculation

= activity factor

T = circuit delay

Ttarget = maximum delay = 1 / frequency


Related work

Related Work

  • 1995: Minimizing Power Consumption in Digital CMOS Circuits

    • Chandrakasan & Brodersen

  • 2005: An Ultra Low Power System Architecture for Sensor Network Applications

    • Hempstead, et al


Conclusion

Conclusion

  • 0.6um best choice for low duty cycle, low frequency operation

  • Problems:

    • PTMs

    • 1.6um


References

References

  • S. Borkar, “Design Challenges of Technology Scaling”, IEEE Micro, vol. 19, no. 4, pp. 23-29, 1999.

  • A. Chandrakasan and R. Brodersen, “Minimizing Power Consumption in Digital CMOS Circuits”, Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, 1995.

  • M. Hempstead, et al, “An Ultra Low Power System Architecture for Sensor Network Applications”, Proceedings of the 32nd International Symposium on Computer Architecture, 2005.

  • Y. Cao, et al, “New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Simulation”, CICC, pp. 201-204, 2000.

  • C. Hu, “BSIM Model for Circuit Design Using Advanced Technologies”, Symp. VLSI Circuits, pp. 5-6, 2001.


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