Introduction to cmos vlsi design lecture 4 dc transient response
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Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response. Credits: David Harris Harvey Mudd College (Material taken/adapted from Harris’ lecture notes). Outline. DC Response Logic Levels and Noise Margins Transient Response Delay Estimation. Activity.

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Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response

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Introduction toCMOS VLSIDesignLecture 4: DC & Transient Response

Credits: David Harris

Harvey Mudd College

(Material taken/adapted from Harris’ lecture notes)


Outline

  • DC Response

  • Logic Levels and Noise Margins

  • Transient Response

  • Delay Estimation

4: DC and Transient Response


Activity

1)If the width of a transistor increases, the current will 

increasedecreasenot change

2)If the length of a transistor increases, the current will

increasedecreasenot change

3)If the supply voltage of a chip increases, the maximum transistor current will

increasedecreasenot change

4)If the width of a transistor increases, its gate capacitance will

increasedecreasenot change

5)If the length of a transistor increases, its gate capacitance will

increasedecreasenot change

6)If the supply voltage of a chip increases, the gate capacitance of each transistor will

increasedecreasenot change

4: DC and Transient Response


Activity

1)If the width of a transistor increases, the current will 

increasedecreasenot change

2)If the length of a transistor increases, the current will

increasedecreasenot change

3)If the supply voltage of a chip increases, the maximum transistor current will

increasedecreasenot change

4)If the width of a transistor increases, its gate capacitance will

increasedecreasenot change

5)If the length of a transistor increases, its gate capacitance will

increasedecreasenot change

6)If the supply voltage of a chip increases, the gate capacitance of each transistor will

increasedecreasenot change

4: DC and Transient Response


DC Response

  • DC Response: Vout vs. Vin for a gate

  • Ex: Inverter

    • When Vin = 0 -> Vout = VDD

    • When Vin = VDD -> Vout = 0

    • In between, Vout depends on

      transistor size and current

    • By KCL, must settle such that

      Idsn = |Idsp|

    • We could solve equations

    • But graphical solution gives more insight

4: DC and Transient Response


Transistor Operation

  • Current depends on region of transistor behavior

  • For what Vin and Vout are nMOS and pMOS in

    • Cutoff?

    • Linear?

    • Saturation?

4: DC and Transient Response


nMOS Operation

4: DC and Transient Response


nMOS Operation

4: DC and Transient Response


nMOS Operation

Vgsn = Vin

Vdsn = Vout

4: DC and Transient Response


nMOS Operation

Vgsn = Vin

Vdsn = Vout

4: DC and Transient Response


pMOS Operation

4: DC and Transient Response


pMOS Operation

4: DC and Transient Response


pMOS Operation

Vgsp = Vin - VDD

Vdsp = Vout - VDD

Vtp < 0

4: DC and Transient Response


pMOS Operation

Vgsp = Vin - VDD

Vdsp = Vout - VDD

Vtp < 0

4: DC and Transient Response


I-V Characteristics

  • Make pMOS is wider than nMOS such that bn = bp

4: DC and Transient Response


Current vs. Vout, Vin

4: DC and Transient Response


Load Line Analysis

  • For a given Vin:

    • Plot Idsn, Idsp vs. Vout

    • Vout must be where |currents| are equal in

4: DC and Transient Response


Load Line Analysis

  • Vin = 0

4: DC and Transient Response


Load Line Analysis

  • Vin = 0.2VDD

4: DC and Transient Response


Load Line Analysis

  • Vin = 0.4VDD

4: DC and Transient Response


Load Line Analysis

  • Vin = 0.6VDD

4: DC and Transient Response


Load Line Analysis

  • Vin = 0.8VDD

4: DC and Transient Response


Load Line Analysis

  • Vin = VDD

4: DC and Transient Response


Load Line Summary

4: DC and Transient Response


DC Transfer Curve

  • Transcribe points onto Vin vs. Vout plot

4: DC and Transient Response


Operating Regions

  • Revisit transistor operating regions

4: DC and Transient Response


Operating Regions

  • Revisit transistor operating regions

4: DC and Transient Response


Beta Ratio

  • If bp / bn 1, switching point will move from VDD/2

  • Called skewed gate

  • Other gates: collapse into equivalent inverter

4: DC and Transient Response


Noise Margins

  • How much noise can a gate input see before it does not recognize the input?

4: DC and Transient Response


Logic Levels

  • To maximize noise margins, select logic levels at

4: DC and Transient Response


Logic Levels

  • To maximize noise margins, select logic levels at

    • unity gain point of DC transfer characteristic

4: DC and Transient Response


Transient Response

  • DC analysis tells us Vout if Vin is constant

  • Transient analysis tells us Vout(t) if Vin(t) changes

    • Requires solving differential equations

  • Input is usually considered to be a step or ramp

    • From 0 to VDD or vice versa

4: DC and Transient Response


Inverter Step Response

  • Ex: find step response of inverter driving load cap

4: DC and Transient Response


Inverter Step Response

  • Ex: find step response of inverter driving load cap

4: DC and Transient Response


Inverter Step Response

  • Ex: find step response of inverter driving load cap

4: DC and Transient Response


Inverter Step Response

  • Ex: find step response of inverter driving load cap

4: DC and Transient Response


Inverter Step Response

  • Ex: find step response of inverter driving load cap

4: DC and Transient Response


Inverter Step Response

  • Ex: find step response of inverter driving load cap

4: DC and Transient Response


Delay Definitions

  • tpdr:

  • tpdf:

  • tpd:

  • tr:

  • tf: fall time

4: DC and Transient Response


Delay Definitions

  • tpdr: rising propagation delay

    • From input to rising output crossing VDD/2 (upper bound)

  • tpdf: falling propagation delay

    • From input to falling output crossing VDD/2 (upper bound)

  • tpd: average propagation delay

    • tpd = (tpdr + tpdf)/2

  • tr: rise time

    • From output crossing 0.2 VDD to 0.8 VDD

  • tf: fall time

    • From output crossing 0.8 VDD to 0.2 VDD

4: DC and Transient Response


Delay Definitions

  • tcdr: rising contamination delay

    • From input beginning to change to output beginning to rise (lower bound)

  • tcdf: falling contamination delay

    • From input beginning to change to output beginning to fall (lower bound)

  • tcd: average contamination delay

    • tpd = (tcdr + tcdf)/2

4: DC and Transient Response


Simulated Inverter Delay

  • Solving differential equations by hand is too hard

  • SPICE simulator solves the equations numerically

    • Uses more accurate I-V models too!

  • But simulations do take time to complete for large circuits

4: DC and Transient Response


Delay Estimation

  • We would like to be able to easily estimate delay

    • Not as accurate as simulation

    • But easier to ask “What if?”

  • The step response usually looks like a 1st order RC response with a decaying exponential.

  • Use RC delay models to estimate delay

    • C = total capacitance on output node

    • Use effective resistance R

    • So that tpd = RC

  • Characterize transistors by finding their effective R

    • Depends on average current as gate switches

4: DC and Transient Response


RC Delay Models

  • Use equivalent circuits for MOS transistors

    • Ideal switch + capacitance and ON resistance

    • Unit nMOS has resistance R, capacitance C

    • Unit pMOS has resistance 2R, capacitance C

  • Capacitance proportional to width

  • Resistance inversely proportional to width

4: DC and Transient Response


Example: 3-input NAND

  • Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

4: DC and Transient Response


Example: 3-input NAND

  • Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

4: DC and Transient Response


Example: 3-input NAND

  • Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

4: DC and Transient Response


3-input NAND Caps

  • Annotate the 3-input NAND gate with gate and diffusion capacitance.

4: DC and Transient Response


3-input NAND Caps

  • Annotate the 3-input NAND gate with gate and diffusion capacitance.

4: DC and Transient Response


3-input NAND Caps

  • Annotate the 3-input NAND gate with gate and diffusion capacitance.

4: DC and Transient Response


Elmore Delay

  • ON transistors look like resistors

  • Pullup or pulldown network modeled as RC ladder

  • Elmore delay of RC ladder

4: DC and Transient Response


Example: 2-input NAND

  • Estimate worst-case rising and falling delay of 2-input NAND driving h identical gates.

4: DC and Transient Response


Example: 2-input NAND

  • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

4: DC and Transient Response


Example: 2-input NAND

  • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

4: DC and Transient Response


Example: 2-input NAND

  • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

4: DC and Transient Response


Example: 2-input NAND

  • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

4: DC and Transient Response


Example: 2-input NAND

  • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

4: DC and Transient Response


Example: 2-input NAND

  • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

4: DC and Transient Response


Delay Components

  • Delay has two parts

    • Parasitic delay

      • 6 or 7 RC

      • Independent of load

    • Effort delay

      • 4h RC

      • Proportional to load capacitance

4: DC and Transient Response


Contamination Delay

  • Best-case (contamination) delay can be substantially less than propagation delay.

  • Ex: If both inputs fall simultaneously

4: DC and Transient Response


Diffusion Capacitance

  • we assumed contacted diffusion on every s / d.

  • Good layout minimizes diffusion area

  • Ex: NAND3 layout shares one diffusion contact

    • Reduces output capacitance by 2C

    • Merged uncontacted diffusion might help too

4: DC and Transient Response


Layout Comparison

  • Which layout is better?

4: DC and Transient Response


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