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DC 相关时序概念 PowerPoint PPT Presentation


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DC 相关时序概念. 主要内容 . 建立时间与保持时间. 扇入与扇出. 时钟. 常用术语. Clock setup :时间建立关系 tsu :输入建立时间 th :输入保持时间 tco :时钟到输出延时 tpd :管脚到管脚延时 Minimum tpd & tco :最小 tpd & tco Clock Skew :时钟偏斜 最小时钟周期与最高频率 Setup Time :建立时间 Hold Time :保持时间 Latency :延迟 Slack :时间裕量. 设计中常用的约束.

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DC 相关时序概念

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Dc

DC


Dc


Dc

  • Clock setup

  • tsu

  • th

  • tco

  • tpd

  • Minimum tpd & tcotpd & tco

  • Clock Skew

  • Setup Time

  • Hold Time

  • Latency

  • Slack


Dc

AssignmentsConstraints3

  • I/O


Dc

  • QuartusIISTASTA


Dc


Path analysis type

Path & Analysis Type


Launch latch edge

Launch & Latch Edge


Dc

Launch Edge

Latch Edge


Clock skew

clock skew

clock skewThe difference in the arrival time of a clock signal at two different registers, which can be caused by path length differences between two clock paths, or by using gated or rippled clocks. Clock skew is the most common cause of internal hold violations.


Dc

skew

  • clock pinSkew


Dc

  • skewglobal skewlocal skewinterclock skew

  • Global skewskew


Dc

  • Local skew2skew


Dc

  • interClock skewskew


Latency

latency

  • Latencysource lantency latency

  • Source latency

  • Latency

  • latency


Latency1

latency

  • latency

  • T2-T1-Tinput_delay-Tsetup


Dc

  • latency

  • T2T2+Tlatency-T1-Tinput_delay-Tsetup

  • DC


Jitter

jitter

  • jitter

  • setup jitter hold jitter


Uncertainty

uncertainty

  • DCskewjitteruncertainty

    set_clock_uncertainty

  • skewuncertainty


Dc

tCLK = Microtco + tLOGIC + tNET + MicrotSU tCLK_SKEW

tCLK_SKEW = tCD2 tCD1

fmax = 1 / tCLK


Dc

Tips

  • setup slack = (<setup relationship>) - (<maximum clock pin to source register delay> + <tCO of source register> + <register-to-register delay> + <tSU of destination register> - <minimum clock pin to destination register delay>)


Dc

  • IC dccellnetdc

  • setup time hold timedc


Dc

  • setup time

  • hold time


Data arrival time

Data Arrival Time


Dc

Launch Edge + Clock path + CellPinPinNetuTco + Data path

Data Arrival Time

+


Clock arrival time

Clock Arrival Time


Slack

Slack

SlackSlackSlack

Slack: Slack is the margin by which a timing requirement was met or not met. A positive slack value, displayed in black, indicates the margin by which a requirement was met. A negative slack value, displayed in red, indicates the margin by which a requirement was not met.

slack = <required maximum point-to-point time> - <actual maximum point-to-point time>


Dc

Launch edgePinPinLatch edge

Data Required TimeLatch edgeData Arrival TimeLaunch edge

Data Arrival TimeData Required TimeData Required TimeData Arrival Time


Dc

ripleSlack


Clock to output delay

(Clock to output delay)

tCO = Clock Delay + MicrotCO +Data Delay


Pin to pin delay

(pin-to-pin delay)

tPD

  • tPD (pin-to-pin delay) The time required for a signal from an input pin to propagate through combinational logic and appear at an external output pin.


Dc

I/O


Dc

tCO tSU tH tPD


Dc


Dc path

DCPath

  • start point

1. input port

2.clock pin of sequential cellclock pin

  • end point

1. output port

2.data pin of sequential celldata pin


Dc

  • 4

path1 input port to data pin of sequential cell

path2 input port to output port

path3 clock pin to data pin of next sequential cell

path4clock pin to output port


Dc

  • dc

  • dc


Dc

  • setup time hold time

  • 20,cell 1, 1, 0.5, slack


Dc

  • dcinput_delay)(output_delay)


Dc

  • Td=Tcell+Td4+Td5+Td6=1+4+3+1=9

  • Td=Tcell+Td4+Td5+Td6+Td8=1+4+3+1+2=11

  • Td=Tcell+Td1+Td2+Td3=1+2+3+2=8

  • Td=Tcell+Td7+Td2+Td3=1+2+3+2=8


Dc

  • hold timeslack Tshortest-Thold=8-0.5=7.5

  • Tlongest=11,Tshortest=8

  • setup timeslackTclk-Tlongest-Tsetup=20-11-1=8


Dc

  • D2 ,D1,TlTs


Set input delay

set_input_delay

  • input_delaydc


Dc

  • ClkAClkDCslack

  • input_delaysetup

Tlogic_delay=Tmin-Tinput_delay-Tsetup

  • dcLogic2


Set output delay

set_output_delay

  • set_output_delay DC


Drive load

DRIVELOAD

  • DCCellnetdelayrcDC

  • delayrccelldrivedriven


Dc

  • bufferloadcapacitanceloadload_of buffer/a,driveresistance

  • 1/R,

  • load

  • dcAPR


Dc

  • celldcinput_transitionout_load

  • netdcwire_load_modelfanout_lengthresistancecapacitance,area


Dc

Wire_load(small){

Resistance : 0.2;

Capacitance : 1.0;

Area :0;

Slop :1.0;

Fanout_length(1, 0.022);

Fanout_length(2, 0.046);

Fanout_length(3, 0.070);

Fanout_length(4, 0.095);

}

  • 2fanout_length20.0460.046capacitanceresistence0.046x1.0,0.046x0.02


Dc

  • 5fanout_length5=fanout_length(4,0.095)+(5-4)*slop=0.095+1*1.0=1.095

  • rctransition=2.2RC


Dc

rc

2.2RC=Rnet+RoutCnet+Cin


Dc

  • dc

  • cellnet

    • cellinput_transitionout_lod

    • netfanout_lengthresistancecapacitanc

  • fanoutloadcapacitancetransitiondelay


Dc design

DCdesign

  • DCchipchipcellchip

  • cell

    • max_fanout

    • fanout_load


Dc

  • AND2designcell(set_driving_cell)AND2max_fanout

    • AND2max_fanout5fanout_load2

    • bufferfanout_load3

  • AND2

    • 2AND2

    • buffer

    • bufferAND2

  • DCDRCfanout_load=2XAND2+buffer=7AND2max_fanout2.


Dc

  • set_max_fanout 5 [all_inputs],set_driving_cellcellmax_fanoutset_max_fanout

  • AND2designfanout_load2

  • dcset_fanout_load [expr [get_attribute slow/and2/a fanout_load] *xxx] [all_outputs]fanout_load


Max fanout max capacitance

Max_fanoutMax_capacitance

  • Max_fanoutfanout_load

  • Max_capacitanceinput port or output port or design load


Fanout delay

fanoutdelay

  • buffernet2buffer1

  • fanout1net3net2

  • 2+1+3+8-12=20


Dc

  • 2+1+2+1+3+4-12=15.

  • 5


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