Ece 4773 team 3a senior capstone lab fall 2006
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ECE 4773 - Team 3A Senior Capstone Lab Fall 2006. SUBSEA BLOW-OUT PREVENTER (BOP) CONTROL MODULE. Team 3a. Name: Rob Warren Position: Project Manager. Team 3a. Name: Mark Shook Position: Configuration Manager. Team 3a. Name: Robert Fenton Position: Correspondent Officer. Team 3a.

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Ece 4773 team 3a senior capstone lab fall 2006

ECE 4773 - Team 3ASenior Capstone Lab Fall 2006

SUBSEA BLOW-OUT PREVENTER (BOP) CONTROL MODULE


Team 3a

Name: Rob Warren

Position: Project Manager


Team 3a

Name: Mark Shook

Position: Configuration Manager


Team 3a

Name: Robert Fenton

Position: Correspondent Officer


Team 3a

Name: Duy Nguyen

Position: Financial Officer


Hydril pressure control
HYDRIL PRESSURE CONTROL

  • Surface

    • Foreman Control

    • Central Processing

  • Sub-Sea

    • Annular BOPs

    • Ram BOPs

    • Control Systems


Requirements
Requirements

  • List of Critical Product Requirements

    • Operate in pressures up to 6700 psi.

    • Operate two solenoids

    • Monitor ram position (LVDT 0-10V)

    • Calculate flow count (5- 100 GPM) via flow meter

    • Communication to external host

    • Capable of testing internal components

    • Modular


Objective
OBJECTIVE

RELIABLE

SUBMERSIBLE

SCALABLE


Design paradigm
DESIGN PARADIGM

  • Communications (TCP/IP)

    • Host to Sub-Sea Unit

      • Fiber Optics

    • Sub-Sea Intranet

      • Ethernet (802.3)


Design paradigm1
DESIGN PARADIGM

  • Logic

    • Field Programmable Gate Array (FPGA)

      • Redundant

      • Reliable

      • Programmable


Design paradigm2
DESIGN PARADIGM

  • Sensor Interface

    • Flow Meter

    • Ram Position Sensor

  • Solenoid Interface

    • Modified H-bridge

      • Dual Direction

      • Solenoid Test

      • H-bridge Test


Hardware system
HARDWARE SYSTEM

Host

LVDT

Main Logic

(FPGA)

A/D converter

Flow Meter

Self Test

Power Interface

(Solenoid)

Solenoids


Software system
SOFTWARE SYSTEM

NET IFACE

NET IFACE

COMMUNICATIONS

BUFFER

BUFFER

BUFFER

LOGIC

CORE

LOGIC

CORE

LOGIC

CORE

MAJORITY

VOTER

SOLENOID

SOLENOID


Software system1
SOFTWARE SYSTEM

NET IFACE

NET IFACE

COMMUNICATIONS

BUFFER

BUFFER

BUFFER

LOGIC

CORE

LOGIC

CORE

LOGIC

CORE

ADC

ADC

ADC

FLOW

METER


Software system2
SOFTWARE SYSTEM

NET IFACE

NET IFACE

COMMUNICATIONS

BUFFER

BUFFER

BUFFER

LOGIC

CORE

LOGIC

CORE

LOGIC

CORE

ADC

ADC

ADC

LVDT


Functional Block Diagram

Clocks

Cond-itioning

ATD

Solenoid Control

Microblaze Processor

Ethernet

Controller

Solenoid Control

Power

Solenoid- 60V

LVDT -10V

H-Bridge- 60V

FPGA- 3.2V

Mini module- 2.5V

A/D converter 3.3V

Mechanical

External pressure (6700 psi)

Size

Functional Block Diagram

Inputs

LVDT

Flowmeter

Network/

(802.3)

Outputs

Solenoid (1)

(2 leads)

Solenoid (2)

(2 leads)

Network/

(802.3)

Power to sensors


Solenoid controller
Solenoid Controller

Solenoid 1

IsolatedSensor

High-VoltageController

CPU

Isolation

IsolatedSensor

Solenoid 2


Timeline
TIMELINE

  • Critical Points

    • Critical Design Review (CDR)

    • Initial Assembly

    • Test Requirement Document (TRD)

    • Final Assembly

    • Testing

    • Project Completion Date


Project Completion Dec. 01

Critical Design Review Oct. 16

Parts Arrive- Initial Assembly Oct. 23

Final Assembly Nov. 10

TRD Nov. 3

Testing Nov. 13




Labor hours analysis
Labor Hours Analysis

  • Weeks 1- 12 were slightly over allocated

  • Weeks 13-15 were under allocated

  • Overall Estimate at completion was under budgeted


Key features performance highlights
Key features/Performance highlights

  • Web user interface

  • Ability to fire both solenoids

  • Ease of interconnectivity/scalability

  • Able to test the H-Bridge and solenoid coil with a trickle current.


Tests via trd
Tests Via TRD

  • Feature Testing

    • Send each software command from the host to the module and verify appropriate action / response

  • Redundancy Testing

    • Disconnect both solenoids, instigate solenoid testing, and verify system failure report

    • Individually disconnect each A/D converter, instigate a position measurement and verify individual system failure report (non-compliant subsystem)

    • Power off 60V power supply, instigate solenoid controller test, and verify system failure report





Recommendations
Recommendations

  • Communication Improvements

The Field Programmable Gate Array (FPGA) is using a Microblaze processor core which is running a sample webserver software package for Ethernet communication. This is a very limited server application and should be improved to allow for greater reliability and versatility. Currently the only means for accessing status information through the control module is by using any standard web browser. This can be very useful, though we recommend when improving the server software concurrently creating a host communication program. This program which would run on any PC or even server class machine could communicate with the control unit on a separate port than the web browser. This would allow for faster more data oriented communications, facilitating improved testing and allowing easier and more frequent collection of sub-sea data such as equipment operability status


Recommendations1
Recommendations

Redundancy

The proposed design called for a highly redundant control unit, using three independent logic cores. These were designed, but not implemented due to time constraints. It is recommended to add these logic cores to the FPGA internal hardware. This Tri-Core technology will create greater redundancy and reliability by using the Microblaze processor solely as the communications driver. The design for this architecture can be located in Appendix 2.


Recommendations2
Recommendations

  • Additional Peripherals

This design is highly scalable with over 100 unused I/O pins. These can be used to easily add the LVDT sensors through external A/D converters including redundant circuitry as well as the flow meter’s pulse train input. In addition, one control module could be configured to operate multiple pairs of solenoids by using an additional optocoupler / H-Bridge circuit for each added pair of solenoids. Multiple sensors could also be added to the control module through unused I/O pins.


Summary
SUMMARY

  • Current System

    • Limited Environment

    • Static

  • Proposed System

    • Reliable

    • Submersible

    • Scalable


Summary1
SUMMARY

  • Straightforward Solution

  • High Level Programming

  • Completed by December 1st


Hydril

HYDRIL

“High Performance Products for Exploration and Production Worldwide”


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