Formal Verification of Candidate Solutions for Evolutionary Circuit Design (Entry 04)

1. Zdeněk Vašíček and Lukáš Sekanina Humies at GECCO 2011 Formal Verification of Candidate Solutions for Evolutionary Circuit Design(Entry 04) Faculty of Information Technology Brno University of Technology Brno, Czech Republic http://www.fit.vutbr.cz/~sekanina THE 8th ANNUAL (2011) “HUMIES” AWARDS FOR HUMAN-COMPETITIVE RESULTS PRODUCED BY GENETIC AND EVOLUTIONARY COMPUTATION HELD AT THE GENETIC AND EVOLUTIONARY COMPUTATION CONFERENCE (GECCO) ON JULY 12–16, 2011 IN DUBLIN, IRELAND

2. Outline • A brief description of the submitted result. • Vasicek Z., Sekanina L.: Formal Verification of Candidate Solutions for Post-Synthesis Evolutionary Optimization in Evolvable Hardware. Genetic Programming and Evolvable Machines, Spec. Issue on Evolvable Hardware Challenges, Vol. 12, 2011, in press • Vasicek Z., Sekanina L.: A Global Postsynthesis Optimization Method for Combinational Circuits. In: Proc. of the Design, Automation and Test in Europe Conference - DATE 2011, Grenoble, EDAA, 2011, p. 1525-1528 • Why our result qualifies as “human-competitive”. • Why we should win a prize.

3. Evolution of combinational circuits • 1993 – Higuchi et al.evolved a 6-input multiplexer • 2000 – Miller et al. showed that the number of gates can be reduced using Cartesian GP w.r.t. the best-known implementations (max. 4-bit multipliers) • Scalability problem – the evaluation time grows exponentially as 2n test vectors have to be applied to evaluate n-input circuit. • The state of the art • The evolutionary design approach works for circuits up to approx. 10 – 20 inputs and approx. 100 gates (depending on circuit). • Improvements w.r.t. the best-known implementations reported only in a few cases. a b c fp 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 n = 3

4. A new fitness function for large circuits Reference circuit is created according to the specification and converted to Conjunctive Normal Form (CNF). Every candidate circuit is converted to CNF. Miter is created and converted to CNF. The MiniSAT solver decides whether a candidate solution and reference circuit are functionally equivalent. If so, fitness = the number of gates.

5. Another improvement of the fitness function • Exploiting the similarity of the parent and offspring  reduction of the CNF size  faster equivalence checking Y/N a small comparator reference circuit mutation a very small CNF candidate circuit The mean evaluation time [ms] in evolution of w-bit multipliers tcgp – standard CGP tsat – fitness with MiniSAT timp – improved eq. checking Ng – seed size (SIS) PI(PO) – primary inputs (outputs)

6. CGP vs. academic and commercial tools LGSynth93 benchmarks – the best obtained number of gates Average reduction: 25% CGP ES(1+1), 1 mut/chrom, seed: SIS, Gate set: {AND, OR, NOT, NAND, NOR, XOR}, 100 runs (each 12 hours) ABC, SIS – conventional open academic synthesis tools C1, C2, C3 – commercial synthesis tools

7. Convergence curves The min, mean and max number of gates out of 50 12-hour runs. max mean min

8. Why our result is “human-competitive” • D: The result of our method is an optimized implementation of a digital circuit (e.g. ALU4) which is typically much smaller than the best result obtained from a conventional synthesis tool. Such solution is publishable in its own right as a new scientific result - independent of the fact that the result was mechanically created - because a clear improvement in the area on a chip can be demonstrated with respect to the state-of-the-art. • E: Because (i) the results of our method are better than the results obtained using the state-of the-art academia as well as commercial tools for a standard circuit benchmark set and (ii) the state-of-the-art tools are based on the best implementations proposed so far, we claim that our solution is equal to or better than the most recent human-created solution to a long-standing problem for which there has been a succession of increasingly better human-created solutions. • G: Despite the fact that various logic synthesis and optimization tools have been proposed in the recent 50 years, the logic synthesis/optimization problem is considered as very difficult. We claim that the proposed method solves a problem of indisputable difficulty in its field.

9. Why we should win (1) • A significant contribution to the evolutionary circuit design and evolvable hardware theory was presented. • We significantly eliminated the scalability problem of the fitness function evaluation which has been known from the very beginning of digital evolvable hardware. • We believe that the approaches based on formal verification techniques could lead to many new applications of evolvable hardware, genetic programming and evolutionary design/optimization. • The result was accepted by the GP/EHW community • Genetic Programming and Evolvable Machines – in its special issue on Evolvable hardware challenges.

10. Why we should win (2) • A significant contribution which has a great impact to applications was presented. • The proposed method is capable of discovering logic circuit transformations that are unreachable by conventional minimization algorithms => better minimization allowed => area/energy/cost savings. • Our contribution is in the field • which is well-established (more than 50 years!), • where extreme competition exists (many companies involved), • which is conservative and pragmatic with respect to completely new approaches and methodologies. • The result was accepted outside the EC community • DATE 2011 – one of the leading conferences in the field of circuit design automation (928 submissions, 34% acceptance rate).

11. Thank you for your attention!