Independence Fault Collapsing and Concurrent Test Generation

1. Master’s Defense Alok S. Doshi Dept. of ECE, Auburn University Independence Fault Collapsing and Concurrent Test Generation Thesis Advisor: Vishwani D. Agrawal Committee Members: Victor P. Nelson, Charles E. Stroud Dept. of ECE, Auburn University January 25, 2006

2. Outline • Introduction • Problem Statement • Motivation • Background • Contributions of this Research • Fault Classification and Independent Faults • Independence Fault Collapsing • Concurrent Test Generation • Simulation Based Techniques • Results • Conclusions and Future Work Alok Doshi: MS Defense

3. Problem Statement To find a minimal test vector set to detect all single stuck-at faults in a combinational circuit. Alok Doshi: MS Defense

4. Motivation a x b c y d e C17 - ISCAS85 Benchmark Circuit 1T. M. Niermann and J. H. Patel, “HITEC: A Test Generation Package for Sequential Circuits,” Proc. European Design Automation Conference, Feb. 1991, pp. 214-218. 2 T. P. Kelsey, K. K. Saluja, and S. Y. Lee, “An Efficient Algorithm for Sequential Circuit Test Generation,” IEEE Trans. Computers, vol. 42, no. 11, pp. 1361-1371, Nov. 1993. 3 W. T. Cheng and T. J. Chakraborty, “Gentest: An Automatic Test Generation System for Sequential Circuits,” Computer, vol. 22, no. 4, pp. 43–49, April 1989. 4H. K. Lee and D. S. Ha, “Atalanta: An Efficient ATPG for Combinational Circuits,” Tech. Report 93-12, Dept. of Electrical Eng., Virginia Poly. Inst. and State Univ., Blacksburg, Virginia, 1993. Alok Doshi: MS Defense

5. Motivation 4-bit ALU (74181) Alok Doshi: MS Defense

6. Background Problem of finding a minimal test: • Static compaction cannot guarantee optimality. • Dynamic compaction is complex. • Solution: Target both faults F1 and F2 at the same time to find a single test. . . . T(F2) T(F1) Test set for fault F2 Test set for fault F1 v2 v1 v3 Alok Doshi: MS Defense

7. Outline • Introduction • Problem Statement • Motivation • Background • Contributions of this Research • Fault Classification and Independent Faults • Independence Fault Collapsing • Concurrent Test Generation • Simulation Based Techniques • Results • Conclusions and Future Work Alok Doshi: MS Defense

8. Fault Classification T(F1) T(F1) = T(F2) T(F2) F1 and F2 are equivalent. F1 dominates F2. T(F1) T(F2) T(F1) T(F2) F1 and F2 are independent. F1 and F2 are concurrently testable. Alok Doshi: MS Defense

9. Definitions Independent Faults5: Two faults are independent if and only if they cannot be detected by the same test vector. Concurrently-Testable Faults: Two faults that neither have a dominance relationship nor are independent, are defined as concurrently-testable faults. 5 S. B. Akers, C. Joseph, and B. Krishnamurthy, “On the role of Independent Fault Sets in the Generation of Minimal Test Sets,” in Proc. International Test Conf., 1987, pp. 1100-1107. Alok Doshi: MS Defense

10. Structural Independences sa1 sa1 sa1 sa0 sa1 sa0 sa1 sa1 sa1 sa0 sa0 sa0 sa1 sa1 sa0 sa0 sa0 sa0 sa1 sa0 Alok Doshi: MS Defense

11. Implied Independences Equivalence implied independence: If two faults are equivalent then all faults that are independent of one fault are also independent of the other fault. Dominance implied independence: If one fault dominates a second fault then all faults that are independent of the first fault are also independent of the second fault. Alok Doshi: MS Defense

12. Functional Independences Alok Doshi: MS Defense

13. Example Circuit 2-1 4-1 a x 5-1 1-1 b 3-1 7-1 c 11-1 y d 6-1 10-1 9-1 e 8-1 C17 - ISCAS85 Benchmark Circuit 6 R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault Collapsing for Multiple Output Circuits," in Proc. Design, Automation and Test in Europe (DATE) Conf., Mar. 2005, pp. 1014 - 1019. Alok Doshi: MS Defense

14. Independence Matrix and Graph C17 - ISCAS85 Benchmark Circuit Alok Doshi: MS Defense

15. Outline • Introduction • Problem Statement • Motivation • Background • Contributions of this Research • Fault Classification and Independent Faults • Independence Fault Collapsing • Concurrent Test Generation • Simulation Based Techniques • Results • Conclusions and Future Work Alok Doshi: MS Defense

16. Independence Fault Collapsing • The aim of independence fault collapsing is to collapse the independence graph into a fully-connected graph such that all or most faults in a given node will have a single test. • These nodes will then serve as fault targets for Automatic Test Pattern Generation (ATPG). Alok Doshi: MS Defense

17. Cliques Alok Doshi: MS Defense

18. Clique A clique is defined as a fully-connected subgraph, i.e., a subgraph in which every node is connected to every other node. A lower bound on the number of tests required to cover all faults of an irredundant combinational circuit is given by the size of the largest clique of the independence graph. Alok Doshi: MS Defense

19. Degree of Independence Degree of Independence: This is the number of edges attached to the fault node and is computed for the ith fault by adding all the elements of either the ith row or the ith column of the independence matrix. DI (ith fault) = Σ xij = Σ xji N N j=1 i=1 Alok Doshi: MS Defense

20. Degree of Independence Alok Doshi: MS Defense

21. Similarity Metric Similarity Metric: This is a measure defined for a pair of faults that determines how similar they are in their independence and concurrent-testability with respect to the entire fault set of the circuit. SIM (fault-i, fault-j) = Nxij + (1-xij) Σ |xik-xjk| N k=1 Alok Doshi: MS Defense

22. Similarity Metrics Alok Doshi: MS Defense

23. Similarity Metric of a Fault-Pair Max. 0 Highly Dissimilar Highly Similar Similarity metric of a fault-pair Equivalent Independent (Group together) (Group separately) Alok Doshi: MS Defense

24. Step 1 – Compute Degree of Independence (DI) for All Faults Alok Doshi: MS Defense

25. Step 2 – Order Faults by DI Alok Doshi: MS Defense

26. Step 4 – Collapse the Graph Step 3 – Compute Similarity Metrics for All Fault-Pairs 11 4 11 3 0 1,8 1 5,11,7 5,11 5 3,9,2 3,9 3 4,6,10 4,6 4 11 0 4 6 Similarity index for fault F for each existing node i: Max. SIM (F, kth fault of node i) where k = 1…..K, and K is number of faults in node i. Alok Doshi: MS Defense

27. Bounds on Number of Tests Nc< Number of tests <Σ where, Nc’ is the number of nodes in the collapsed graph (Nc’ ≥ Nc). and, ki is the number of faults in the ith node. For C17, 4 < Number of tests < 7. Nc’ ki _ i=1 2 Alok Doshi: MS Defense

28. Outline • Introduction • Problem Statement • Motivation • Background • Contributions of this Research • Fault Classification and Independent Faults • Independence Fault Collapsing • Concurrent Test Generation • Simulation Based Techniques • Results • Conclusions and Future Work Alok Doshi: MS Defense

29. Concurrent Test Generation Concurrent Test: Given a set of target faults, a concurrent-test is an input vector that detects all (or most) faults in the set. Alok Doshi: MS Defense

30. Concurrent D Algebra for 2-Input AND Gate Alok Doshi: MS Defense

31. Concurrent Test Generation for C17 D2 D2 0 D23 2-1 D3 1 D3 3-1 D39 1 0 1 9-1 D9 1 D9 Alok Doshi: MS Defense

32. Concurrent Test Generation for C17 2-1 4-1 a x 5-1 1-1 b 3-1 7-1 c 11-1 y d 6-1 10-1 9-1 e 8-1 Alok Doshi: MS Defense

33. Results (ALU – 74181) Alok Doshi: MS Defense

34. Outline • Introduction • Problem Statement • Motivation • Background • Contributions of this Research • Fault Classification and Independent Faults • Independence Fault Collapsing • Concurrent Test Generation • Simulation Based Techniques • Results • Conclusions and Future Work Alok Doshi: MS Defense

35. Simulation-Based Techniques • The functional dominance fault collapsing6, used prior to independence fault collapsing, is based on ATPG and is complex. • The independence graph generation procedure is also based on ATPG. • The use of concurrent D-algebra requires a new ATPG program that may not be readily available to a user. 6 R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault Collapsing for Multiple Output Circuits," in Proc. Design, Automation and Test in Europe (DATE) Conf., Mar. 2005, pp. 1014 - 1019. Alok Doshi: MS Defense

36. Simulation-Based Independence Fault Collapsing • Start with a fully-connected independence graph for an equivalence collapsed fault set (structural collapsing only), i.e., assume initially all faults are independent of each other. • Simulate random vectors without fault dropping to remove edges between faults detected by the same vector. Stop the random vector simulation when a large number of vectors do not remove any new edges. • Apply the original independence fault collapsing algorithm on the generated independence matrix. Alok Doshi: MS Defense

37. Simulation-Based Independence Fault Collapsing 301 74181 4-bit ALU Alok Doshi: MS Defense

38. Simulation-Based Concurrent Test Generation • For each group, generate all test vectors for the first fault in the group. • If the number of test vectors for a fault is large, use a subset (e.g., 250 maximum) of vectors. • Simulate all faults in the group to select one vector that detects most faults in that group. • If more vectors than one detect the same number of faults within the group, then select the vector that detects most faults outside the group as well. Alok Doshi: MS Defense

39. 74181 4-Bit ALU Result Alok Doshi: MS Defense

40. Outline • Introduction • Problem Statement • Motivation • Background • Contributions of this Research • Fault Classification and Independent Faults • Independence Fault Collapsing • Concurrent Test Generation • Simulation Based Techniques • Results • Conclusions and Future Work Alok Doshi: MS Defense

41. Concurrent ATPG Results * Sun Ultra 5 *** Pentium Pro PC ** Hamzaoglu and Patel, IEEE-TCAD, 2000 Alok Doshi: MS Defense

42. Number of Vectors for Increasing Circuit Sizes (100% Stuck-at Coverage) Single-fault ATPG (no compaction) Concurrent ATPG Minimum achieved! (dynamic compaction) 1-bit c7552 adder Alok Doshi: MS Defense

43. CPU Seconds for Increasing Circuit Sizes (100% Stuck-at Fault Coverage) Concurrent ATPG Minimum achieved! (dynamic compaction) 1-bit c7552 adder Alok Doshi: MS Defense

44. Outline • Introduction • Problem Statement • Motivation • Background • Contributions of this Research • Fault Classification and Independent Faults • Independence Fault Collapsing • Concurrent Test Generation • Simulation Based Techniques • Results • Conclusions and Future Work Alok Doshi: MS Defense

45. Conclusions • Concurrent test generation produces compact tests when combined with independence fault collapsing. • ATPG and set covering problems have exponential time complexities. Hence, we cannot expect absolute optimality for large circuits. • The concurrent ATPG procedure gives significantly smaller, and sometimes the optimum, test sets. Alok Doshi: MS Defense

46. Future Work • There is scope for improving the simulation-based algorithms for independence fault collapsing and concurrent test generation. • Can be made more dynamic. • Concern about memory requirement. • Implement an ATPG program using the concurrent D algebra. Alok Doshi: MS Defense

47. Future Work – Another Collapsing Technique 3 11 4 11 5 6, 5, 11 6 7 7, 1 7, 1, 10 6, 5 8 9, 3, 2 9 8, 4 9, 3 11 4 4 0 6 11 Alok Doshi: MS Defense

48. Thank You! Alok Doshi: MS Defense