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VIPIX ( V ertically I ntegrated PIX els) Attivita’ e Richieste 2012

VIPIX ( V ertically I ntegrated PIX els) Attivita’ e Richieste 2012. SUNTO: Programma scientifico: WP1 : sensori ed elettronica di FE WP2 : TDAQ WP3 : Integrazione/meccanica/Test-beam Attivita’ 2011 per I 3 WP Programma 2012 Richieste ai Servizi di Sezione Manpower Conclusioni.

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VIPIX ( V ertically I ntegrated PIX els) Attivita’ e Richieste 2012

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  1. VIPIX(Vertically Integrated PIXels)Attivita’ e Richieste 2012 SUNTO: • Programma scientifico: • WP1 : sensori ed elettronica di FE • WP2 : TDAQ • WP3 : Integrazione/meccanica/Test-beam • Attivita’ 2011 per I 3 WP • Programma 2012 • Richieste ai Servizi di Sezione • Manpower • Conclusioni G. Rizzo per il gruppo VIPIX-Pisa INFN – Pisa, 14 Giugno 2011

  2. Progetto VIPIX Vertically Integrated PIXel • Scopo • Sviluppare sistemi a pixel per tracciatori sottili di particelle cariche basati su tecnologie di integrazione verticale • sottile: sensore+front-end ma anche supporto e cooling • sistema: sistema di memorie associative per trigger di traccia di LV1 • Richiesto il prolungamento ad un IV anno per portare a termine le attivita’ in corso. • Sezioni coinvolte: BO, MI, PI, PG, PV/BG, RM3,TN (PD),TS~15 FTE • Il progetto VIPIX ha finalita’ simili a quelle perseguite con successo nel corso del progetto SLIM5ma punta su una soluzione tecnologica molto innovativa (Vertical Scale Integration) per migliorare le performance dei pixel attivi monolitici (e.g. CMOS MAPS) sviluppati fino ad oggi e per esplorare la possibilita’ di realizzare pixel sottili su alta resistivita’. • Il gruppo riunisce tutte le sezioni che fanno ricerca sulle MAPS in Italia.

  3. VIPIX: Struttura ed attivita’ WP 1: coord. G.Rizzo (L.Ratti deputy) “Pixel ad integrazione verticale” Studio/design dell’architettura di readout per MAPS in VI e FE per pixel ibridi Layout delle matrici di cui sopra Produzione schede di test dei chip realizzati Caratterizzazione dei prototipi (test funzionali, laser, sorgenti) WP 2: coord. M.Villa “Trigger/DAQ” Upgrade delle Edro e AM board, LV1 trigger studies WP 3: coord. S.Bettarini “Integrazione, meccanica e testbeam” Sviluppo meccanica e cooling “sottile” mediante microcanali realizzati su supporti ceramici/CF e integrati direttamente su wafer di silicio Test prototipi Integrazione e organizzazione beam test By FBK-IRST 3

  4. MAPS & Vertical Integration Technologies VIPIX plans to pursue two different basic approaches: • Interconnection between 2 CMOS layers, one layer with a MAPS (DNW) device and analog front-end and the other layer with the digital readout • Interconnection between a CMOS readout electronics chip (2D or 3D) and a fully-depleted high resistivity sensor with bump bonding (standard) or with a vertical integration technique (low material budget, more advanced) 3D MAPS 2D MAPS

  5. CMOS MAPS con integrazione verticaleRUN PILOTA 2009 • Primi dispositivi MAPS realizzati su 2 layers (analogico/digitale) run Chartered/Tezzaron 130 nm. Apsel-like test structures (analog tier) – PI,PV/BG Apsel-like test structures (digital tier) Apsel-like 8x32 matrix (analog tier) – BO,PI,PV/BG Apsel-like 8x32 matrix (digital tier) 3D Digimaps (digital tier) 3D Digimaps (analog tier) – Roma3 2D test structure – Roma3 5.5 mm 6.3 mm 6.3 mm ANALOG TIER DIGITAL TIER Multilayer sensor - PG Multilayer sensor

  6. DELAY/Status run pilota 2009 …endless mistake reports by R.Yarema (Fermilab) Ready for submission mid 2009 Wafer fabrication started only in march 2010 after several months of delay. May 2010 - Chartered difficulties in completing the TSV processing. Oct 2010 – Chartered wafers produced with reticules offset  no 3D assembly possible. New wafer processed!  • March 2011: first attempt to perform Cu-Cu 3D wafer bonding by Tezzaron • 3 wafer pairs were bonded and all three had large unbonded areas in the center of the wafer pairs. The problem was found (by Ziptronix) in a layer of 3-7 nm of Carbon. • After removing the residue, the unbonded wafers were sent back to EVG in Tempe for bonding. Newly fabricated wafer with proper frame placement on the wafer May 17 (2011): two new wafers pairs were bonded by EVG with better bonding results. Thinning is the next step, followed by back metal deposition Tutte le attivita’ legate al test di queste strutture e a run successivi nella tecnologia Tezzaron/Chartered hanno subito un notevole ritardo. 6

  7. Riassunto attivita’ WP1 (I) • Run pilota sottomesso nel 2009 con strutture MAPS evoluzioni di APSEL4D non completamente ottimizzate per approccio 3D (dettagli nelle slide backup) • Gravi ritardi nella produzione del run pilota, ma nel frattempo l’attivita’ e’ proseguita sulle due linee di attivita’ con risultati significativi. • Realizzazione Superpix0: chip di FE per pixel ibridi (32x128 pixels, 50 um pitch, ST 130 nm) interconnesso con bump-bonding a pixel n su p (FBK). ENC=80 e-, S/N=200 Preparazione I sottomissione VIPIX • MAPS APSELVI (128x96) e FE HP Superpix1(32x128) 50 um pitch e stessa architettura di readout (data push & triggered) ottimizzata per Layer0 SuperB • Strutture DIGIMAPS e APS a piccolo pitch

  8. TSComp. DATA-OUT HIT-OR-OUT Exploiting 3D integration for next submission: in-pixel logic with time-stamp latch for a time-ordered readout F. Morsani • No Macropixel • Timestamp (TS) is broadcast to pixels & pixel latches the current TS when is fired. • Matrix readout is timestamp ordered • A readout TS enters the pixel, and a HIT-OR-OUT is generated for columns with hits associated to that TS. • A column is read only if HIT-OR-OUT=1 • DATA-OUT (1 bit) is generated for pixels in the active column with hits associated to that TS • More in pixel logic possible with 3D integration • Readout could be data push or triggered

  9. Riassunto attivita’ WP1 (II) Preparazione della I sottomissione VIPIX • Design cella analogica per MAPS e FE pixel ibridi (dettagli slide backup) • Ottimizzazione architettura di readout per sfruttare maggior spazio per logica in-pixel: • storing timestamp nel pixel e lettura ordinata temporalmente, rimozione MP • simulazione VHDL readout data push e triggered con target hit rate 100MHz/cm2 su full chip size (1.3 cm2) • Triggered: readout effi ~ 98.2 % (6 us trigger latency) dead time during trigger latency for pixel already fired • Data push effi> 99.9% with 50 MHz clock

  10. Riassunto attivita’ WP1 (III) First results on MAPS from Chartered/Tezzaron process • Da diversi mesi pronti per gli step finali della sottomissione ma in attesa delle strutture 3D run pilota. Digital tier Sensor + analog tier • A Marzo 2011 caratterizzazione prime strutture Chartered/Tezzaron 2D (solo layer analogico): risultati promettenti. Preliminary • ENC ~ 45 e- • Calibration with Fe55 • Gain ~ 300 mV/fC from 5.9 keV peek. • First estimate of MIP signal from test with Sr90 ~ 850 e-

  11. Riassunto attivita’ WP1 (IV) Realizzazione di MAPS 2D con processo INMAPS: • stessa architettura di readout ottimizzata per 3D (piu’ logica in-pixel grazie al layer digitale) • Processo con quadrupla well che scherma raccolta carica di n-well parassite in competizione con elettrodo di raccolta • disponibile substrato ad alta resistivita’ per miglior raccolta di carica e resistenza alla radiazione. • Sottomissione in corso con matrici 32x32 con readout digitale e 3x3 analogiche • Alcuni “sottoprodotti” importanti dell’attivita’ VIPIX FE chip per lettura strip SuperB: • Adattamento dell’architettura sviluppata per i pixel 3D per lo sviluppo dei chip di lettura delle strip dell’ SVT di SuperB

  12. WP 2: “AM-Trigger/DAQ” Attivita’ svolta a Pisa fino ad oggi: Produzione/test LAMBs per attrezzare la scheda con piu’ memoria associativa: abbiamo 2 schede di memoria associativa completamente attrezzate di LAMBs con cui fare tests di confronto Design della nuova scheda con features di auto debugging: prodotta, in attesa di DC-DC converters la cui produzione e’ ritardata dal disastro del Giappone. Design di nuova scheda, molto avanzata, con i piu’ moderni FPGAs ed uso avanzato di link seriali, in corso. Goal: 80 MHz di input e grossa potenza per utilizzare molta memoria associativa. La mancanza di performance sopra 40 MHz era un problema di power. Per il test-beam 2011: realizzato backplane nuovo e piu’ affidabile che permette alle due schede di stare in un unico crate sotto un solo software di gestione ! Importante per una piu’ efficiente presa dati sulle piccole matrici (150umx150um, 3x3 pixels) da caratterizzare su fascio. Problemi di manpower per gestire le banche a causa di perdita di personale. Si-detectors AM EDRO Upgrade di trigger-DAQ per estenderne le performance rispetto a SLIM5

  13. New TEST SETUP integrated in one crate Downloading hits from VME into input FIFOs AMBOARD EDRO SOFTWARE developed in Pisa (Run Control application & Monitoring Software) integrated in the same partition with the EDRO one developed in Bologna Tested simple monitoring functions No high frequency failures Data (hits & roads) written on disk for analysis and search of low frequency failures 13

  14. WP 3: Meccanica/Integrazione/Test-beam Integrated cooling realized on the Silicon wafer For the VIPIX R&D experiment we are testing DIRECT COOLING in a silicon chip. This is a collaboration with the FBK of Trento (Italy) in the agreement INFN PAT MEMS2 to realize in DRIE process these special microchannels. A DRIE process is used to obtain a special shape trenches in the silicon. These original shape allows an easy sealing of the microchannel with very thin layer semiconductor oxide (PECVD). trench We expect : • No heath sink • High power removed • High drop pressure microchannel

  15. Microchannel integration on silicon prototype Two different mask designs to obtain microchannel Dh = 50 mm and 100 mm A) transversal strip B) longitudinal strip At the moments we are testing prototypes type B) with Dh=50 mm Silicon longitudinal section Silicon transversal section

  16. Microchannel integration on silicon prototype From a 4” wafer are obtained N.5 silicon prototypes of 12.8 width mm x 60 mm length x 500 mm thick with N.61 microchannel to perform cooling tests at the TFD lab in order to measure hydraulic and thermal parameters. 500 mm 4.2 mm 150 mm Silicon oxide sealing 60 mm This geometry realized also on 200um thick Si samples

  17. Microchannels on silicon prototype test at the TFD test-bench In the test set-up, the hydraulic interface is the same used for CFRP microchannel module, the sample is configured with kapton heather on one side and N.3 temperature probes on the opposite side; coolant is water-glycol 50% @ 10 °C . . . Kapton heater Silicon Microchannel Hydraulic interface Temperature probes We are completing tests on various prototypes. Oxide sealing works up to pressure of 100 Atm without leak. We learnt that handling is critical for the 200 um thick prototypes.

  18. Prototype test results Temperature along the silicon module at the different power Temperature along the silicon module at the different pressure W=2 W/cm2 Dp=3.5 atm Silicon module temperature strongly dependent from the value of coolant flow .

  19. VIPIX/SuperB Test Beam(@CERN-SPS): 120 GeV p+/- s2resolution = s2residual - s2extr-track - s2MS on DUT Telescope with 2+2 moduli Telescope with 3+3 moduli 4+1 Telescope modules under Construction by TS (now in Pisa for bonding) Schedule: BIG-MD inside our period In touch with RunCo to get more beam-time.

  20. Layout of the “demonstrator” T4-5-6 T1-2-3 SC SC DUT: Striplets Analog MAPS V.I. MAPS Hybrid pixel MAPS PG X-Y sides X-Y sides Movable-table Telescope hits available (offline) for track-reconstructions for MAPS-PG DAQ PG (and PI for analog maps) synchronized to the main DAQ High P and small divergence beam necessary for test of small sensor  SPS

  21. Test-Beam 2011: DUTs list • 3x3 matrices apsel3T1 for efficiency measurement before and after neutron irradiation. • Hybrid pixel det: superpix0 (32x128) bump-bonded to High-W pixel det. for efficiency/resolution vs THRs and angle scan: • carrier mounted on the apsel4D PCB • under test the feasability to run the DAQ with ¼ of the matrix at a time (known r.o. feature of the chip) • fiducial region CUT for (for efficiency) • “V.I.” MAPS (pilot run) for efficiency measurement • 3x3 matrices (called 5T_3D) on 2D wafer • carrier per PCB of 5T • Striplets Module: under test in 2008. Further studies needed (lower THRs and 45o70o angle) • Apsel4D(1): MAPS 32x128 matrix under test in 2008. Under test in 2008. Statistics needed for 45o70o angle scan. • Associative Memories test (flag or active). They might be useful (not mandatory) to provide a more efficient trigger with small matrices w.r.t. TB2009 • Detailed schedule on system test on spare slides.

  22. Programma attivita’ VIPIX 2012 • Chiediamo la prosecuzione di una anno per completare le attivita’, a causa dei gravi ritardi del run pilota, ed effettuare test sul run VIPIX previsto ~ fine 2011: • WP1: • test di caratterizzazione strutture realizzate • Irraggiamento (g e n) delle strutture di tests • Test di interconnessione verticale chip FE 3D con pixel high res. • WP3: • Concludere in modo sistematico i test su altri campioni con maschera#2 da FBK • E’ stata acquisito un wafer 8” con strutture Chartered/Tezzaron 2D su cui ricavare 2 water da 4” da sottoporre a FBK a DRIE ecthing per dimostrare: • Il processo DRIE e’ compatibile con il processo CMOSle prestazioni (S/N) non cambiano. • IDEM in condizioni operative sotto flusso di liquido (non si sviluppano tensioni meccaniche tali da modificare le performance). Necessario un pitch adapter con la PCboard di test del “modulo idraulico”

  23. Elettronica: Morsani: 30% Design CMOS in VI Realizzazione carriers/test boards Test-beam Progettazione Meccanica/Alte Tecnologie: Bosi: 10% Design/FEA/caratterizzazione TFD prototipi u-canali integrati su wafer di Si Disegnatore: Aiuto nella produzione dis. esecutivi per realizzazione prototipi/features (tipo interfacce idrauliche) per l’officina e piccoli supporti meccanici Tecnici Alte Tecnologie: 0.3 FTE Test prototipi TFD micro-saldatura ed incollaggio chip Officina: 0.3 FTE Realizzazione piccoli supporti meccanici e interfacce idrauliche Richieste ai servizi di sezione 2012

  24. Personale e Percentuali (~definite) • 6 Fisici -> 2.0 FTE Fisici Richieste tecnologi:

  25. Backup

  26. Same architecture will be implemented in 3D MAPS and 3D FE chip for Hybrid pixel Vertical Integration (3D) technology options for the SuperB Layer0 INFN - VIPIX collaboration from 2D to 3D MAPS • less PMOS in the sensor layer • improved collection efficiency • more room for in-pixel logic • improved readout architecture • analog and digital blocks in 2 tiers • minimize cross-talk • more room for both analog and digital power and signal routing • Tier 1: sensor + analog front-end + part of the discriminator • Tier 2:part of the discriminator + digital front-end + peripheral readout electronics 3D Hybrid Pixel detector • high resistivity sensor • larger signal • better trade off between S/N and dissipated power • radiation hard • 3D front end chip: (2 tiers=more room for in-pixel logic) to be connected to high res. sensor with more (bump bonding) or less (direct bonding) standard technique

  27. Digital section 2nd wafer 2nd tier 1st tier 1st wafer Deep N-well sensing electrode Analog section The first 3D CMOS MAPS in the APSEL family 3D MAPS Chartered/Tezzaron technology (Fermilab MPW run) • first APSEL-like DNW MAPS (2 tiers) realized within the 3DIC Consortium to explore the 130 nm Chartered/Tezzaron process. Run still ongoing! • Test structures → 3x3 analog matrix - first optimization of analog cell and sensor layout for 3D version • 8x32 MAPS matrix with APSEL4D readout architecture • data-driven sparsified readout + timestamp; MacroPixel based • in next version improved architecture exploiting 3D (i.e. remove MacroPixel)

  28. Analog front-end for 3D monolithic and hybrid pixels shift-in shift-out C2 C2 Front-end for MAPS Design features and simulation results W/L=32/0.25, ID,PA=15 mA THR DAC Total power dissipation=37 μW A(s) CD=300 fF C1 C1 375 ns peaking time Charge sensitivity: 730 mV/fC VTHR VGTHR VREF ENC: 33 electrons CF CF Threshold dispersion: 60 electrons MIP Signal ~ 1000 e- Front-end for hybrid pixels Design features and simulation results W/L=18/0.25, ID,PA=2.5 mA Total power dissipation=7 μW CD=150 fF 300 ns peaking time Charge sensitivity (GQ): 45 mV/fC ENC: 130 electrons Threshold dispersion: 380 e- MIP Signal ~ 16000 e-

  29. Results on Superpix0 • Gain(by Cinj scans): • 38.0 mVfC with sensor (6 % dispersion), 40.9 mV/fC w/o sensor (5 %) • Noise (ENC= RMSnoise/Gain): • 66 e- w/o sensor , 81 e- with sensor  S/N = 200! • Threshold dispersion (RMSbaseline/Gain): • 478 e- w/o sensor - 482 e- with sensor • Pixel threshold tuning circuit implemented in the next design

  30. DELAY/Status run pilota 2009 …endless mistake reports by R.Yarema (Fermilab) • Tezzaron uses a “via first” approach for the fabrication of 3D chip. • Chartered: difficulties in completing the TSV processing. After TSV fabrication and filling, a chemical is used to strip the mask. The striping process has been eating into the top of the tungsten filled via leaving a dip in the surface.  • New wafers had 400 nm of protective nitride, removed from surface and then were sent to EVG in Tempe for bonding. 3 wafer pairs were bonded and all three had large unbonded areas in the center of the wafer pairs. • The problem was found (by Ziptronix) in a layer of 3-7 nm of Carbon. • After removing the residue, the unbonded wafers were sent back to EVG in Tempe for bonding. • May 17 (2011): two new wafers pairs were bonded by EVG with better bonding results. Thinning is the next step, followed by back metal deposition Newly fabricated wafer with proper frame placement on the wafer Tutte le attivita’ legate al test di queste strutture e a run successivi nella tecnologia Tezzaron/Chartered hanno subito un notevole ritardo. 31

  31. 3D Fabrication Issues A lot of 31 wafers was fabricated Due to delays in fabrication, the 3D wafer bonding facilities were not available when the batch of wafers were ready. New wafers had 400 nm of protective nitride removed from surface and then were sent to EVG in Tempe for bonding at about 240 lb/in2 and 400 degrees C. Newly fabricated wafer with proper frame placement on the wafer R. Yarema, FEE2011, Bergamo, May 2011 SuperB Workshop and kick-off meeting, Elba, May 31, 2011 32 V. Re

  32. 3D Fabrication Issues After the nitride removal, three wafer pairs were bonded and all three had large unbonded areas in the center of the wafer pairs. There was not sufficient bond strength to continue with grinding one of the bonded wafers to 12 um because the wafers would break. The problem was thought to be either a small amount of nitride which was not removed or problems with the bonding machine. The unbonded wafers were sent to another EVG facility while the bonded pairs were sent to Ziptronix for analysis. One wafer pair was broken to expose the center and using a SEM a 3-7 nm thick layer was found on the wafer surface. At first the layer was thought to be nitride but an Auger electron microscope chemical analysis showed that the layer was carbon. All the unbonded wafers were then returned to Ziptronix where the carbon layer has been removed. After removing the residue the unbonded wafers were sent back to EVG in Tempe for bonding. By May 17 two new wafers pairs were bonded by EVG with better bonding results. Thinning is the next step, followed by back metal deposition carbon SEM image showing 3-7 nm residue on wafer surface R. Yarema, FEE2011, Bergamo, May 2011 SuperB Workshop and kick-off meeting, Elba, May 31, 2011 33 V. Re

  33. Acoustic Microscope Image of 3D bonded Wafers Poorly bonded wafer pair Good bonded wafer pair R. Yarema, FEE2011, Bergamo, May 2011 SuperB Workshop and kick-off meeting, Elba, May 31, 2011 34 V. Re

  34. Monolithic Active Pixel Sensors in the INMAPS process (CMOS 180 nm) The deep P-well can be used to prevent parasitic charge collection by n-wells competing with the sensing electrode The technology provides epitaxial layers 5 or 12 mm thick with a maximum resistivity of 50 Ω*cm High resistivity epitaxial layers (1 kΩ*cm) 12 or 18 mm thick are also available. Deep P-well combined with high resistivity epi-layer increases the charge collection efficiency. This makes it possible to use a simple nwell diode instead of a large DNW sensor, reducing the overall noise.

  35. The board for 128 AM chips working at full rate Patio to host DC-DC converters No space for them below the LAMBs 25 A 25 A 25 A 25 A 25 A 25 A S. Bettarini

  36. Test-beam 2011: next steps(according to our past experience in 2008) • System TEST in BO: • DAQ already able to perform tests with a superpix0 chip • Table already mounted (10/5) • 2008 stuff (old telescope modules, black and blue cables, crates, …) transferred from TS on 8-10/6 • Starting on the 27th of june in Bo: • Install motor switches and operate movable table • Mount new mechanical holder for Telescope and DUTs • Installation of Power Supply, monitoring, ilk, new dry-air manifold • Optimize calibrations vs time (digital pixel and striplets) • Analog maps test (DAQs synchronized as in 2008) • AM integration and implement small matrix trigger ? • At the beginning of September: • Perform latest DAQ tests • Dismount & package all the system • Fix the parts of the table and insert it in the shipping box(80cmx160cm, h=120cm ): we’ll save time/work wrt 2008! • Checklist for CERN readiness

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