1 / 14

Activity at IDA

Activity at IDA. Mircea Negrean. Activity at IDA. Since July 2007 Research Project: IDA – Bosch ( Confidential ) Activity at IDA Research of multiprocessor scheduling, synchronization, … Extension of SymTA/S framework

stacy
Download Presentation

Activity at IDA

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Activity at IDA Mircea Negrean Institute of Computer and Communication Network Engineering

  2. Activity at IDA • Since July 2007 • Research Project: IDA – Bosch (Confidential) • Activity at IDA • Research of multiprocessor scheduling, synchronization, … • Extension of SymTA/S framework • Static Priority Preemptive scheduler considers now the blocking time computed according to MPCP. • Hiwi mentoring together with Simon Schliecker • Paper Reviews

  3. MultiprocessorScheduling and Blocking TimeAnalysis Mircea Negrean Simon Schliecker Rolf Ernst Institute of Computer and Communication Network Engineering

  4. Outline • Moving to multicore ECUs • Multiprocessor scheduling and blocking time analysis • Integration in SymTA/S - Demo

  5. Moving to multicore ECUs (1) • Virtualization • Partitioned scheduling • Reuse of already known uniprocessor techniques, code reuse, a.s.o. ECU2 ECU1 ECU CPU2 CPU1 CPU2 CPU1 CAN1-IF CAN2-IF CAN1-IF CAN2-IF Multicore ECU architecture Distributed multiprocessor architecture

  6. Moving to multicore ECUs (2) • Problem • Sharing global resources leads to interference across cores • Architectures must support real-time • Requirements • Protocols which cover • Tasks scheduling on each core • Resource arbitration ECU CPU2 CPU1 CAN1-IF Multicore ECU Architecture (with shared resources)

  7. Multiprocessor Priority Ceiling Protocol (MPCP) • Extension of uniprocessor PCP [Rajkumar90] • Assumptions and Definitions: • Static assignment of tasks to processors and local scheduler on each core • Global priority space on the multiprocessor system • Local resources • used only by tasks mapped on the same core • Global resources • used by tasks mapped on different cores • Priorities of global resources are higher than priorities of all tasks in the multiprocessor system • Nesting of local and global resources is not allowed

  8. CPU1 CPU2 CAN-IF T2 T1 L1 L2 R T3 T4 Types of blocking on multicore ECU • Local blocking time (PCP) • Due to lower priority local tasks • Blocking due to • remote tasks • higher priority gcs's which can preempt lower priority gcs's on remote cores • lower priority local tasks which may perform request to global resources when the analyzed task becomes suspended Local Resources Global Resources

  9. Tasks’ worst-case response time analysis WCRT(T3) T1 CAN-IF CPU1 T3 R R Shared Resources CAN-IF T2 T1 R T3 T4 T2 CAN-IF CPU2 T4 R t

  10. Demo Multiprocessor scheduling and blocking time analysis in SymTA/S

  11. Multiprocessor analysis in SymTA/S (1) • No shared resources on the ECU ECU CPU1 CPU2 T3 T2 T5 T4 T7 CAN1-IF CAN2-IF

  12. Multiprocessor analysis in SymTA/S (2) • Cores share the CAN-Interface ECU CPU1 CPU2 T3 T2 T5 T4 T7 System non-schedulable CAN1-IF

  13. Multiprocessor analysis in SymTA/S (2) • Assign higher priority to T5 (T5 -> T1) ECU CPU1 CPU2 T3 T2 T1 T4 T7 System is schedulable CAN1-IF

  14. Thank you …

More Related