An automatic tool flow for the combined implementation of multi-mode circuits

1. An automatic tool flow for the combinedimplementation of multi-mode circuits Brahim Al Farisi, KarelBruneel, Joao M. P. Cardoso and Dirk Stroobandt DATE’13

2. OUTLINE • 1.INTRODUCTION • 2. RUN-TIME RECONFIGURATION • 3. GENERATING A PARAMETERIZED CONFIGURATION FOR MULTI-MODE CIRCUITS • 4. EXPERIMENTS AND RESULTS • 5. CONCLUSION

3. INTRODUCTION • run-time reconfiguration (RTR) • The inherent reconfigurability of SRAM-based FPGAs enables the use of different configurations at different time intervals. • Using RTR, global area can be reduced by reusing FPGA resources between circuits. • reconfiguration time • change between these functions a period of time is needed, to rewrite the configuration memory

4. INTRODUCTION • The conventional way of building RTR systems needs to be rewritten, this often leads to very long reconfiguration times [2]. • multi-mode circuit • the functionality of a limited number of circuits, of which at any given time only one needs to be realised

5. RUN-TIME RECONFIGURATION • A. Modular Dynamic Reconfiguration[1] • When implementing a multi-mode circuit with MDR, every mode will be placed in a separate module.

6. RUN-TIME RECONFIGURATION • B. Dynamic Circuit Specialization[3]

7. GENERATING A PARAMETERIZED CONFIGURATION FOR MULTI-MODE CIRCUITS

8. GENERATING A PARAMETERIZED CONFIGURATION FOR MULTI-MODE CIRCUITS • Merging of several LUT circuits into a Tunable circuit consists of two steps: • 1) determine which LUTs will be implemented using the same Tunable LUT

9. GENERATING A PARAMETERIZED CONFIGURATION FOR MULTI-MODE CIRCUITS • 2) the annotation of the connections with the appropriate activation function to generate the Tunable connections.

10. GENERATING A PARAMETERIZED CONFIGURATION FOR MULTI-MODE CIRCUITS

11. GENERATING A PARAMETERIZED CONFIGURATION FOR MULTI-MODE CIRCUITS • A. Combined placement • The conventional placement tool is based on simulated annealing • only one LUT is allowed per physical LUT • New placement tool to accommodate the simultaneous placement of several LUT circuits • LUTs belonging to different modes can be placed on the same physical LUT.

12. GENERATING A PARAMETERIZED CONFIGURATION FOR MULTI-MODE CIRCUITS • B. Optimization options • circuit edge matching • reduce the number of Tunable connections by placing the LUTs of the different modes in such a way that the number of connections that have the same source and sink is maximized • Circuit edge matching [6]only looks at the topology of the Tunable circuit that is formed and does not take into account the placement of the Tunable LUTs.

13. GENERATING A PARAMETERIZED CONFIGURATION FOR MULTI-MODE CIRCUITS • wire-length optimization • the cost function used in the wire-length optimization approach uses an estimation of the wire length TRoute will need to route the Tunable circuit.

14. EXPERIMENTS AND RESULTS • A. Benchmarks

15. EXPERIMENTS AND RESULTS • B. FPGA architecture • The combined placement algorithm was implemented based on our Java version of the VPR (Versatile Place and Route) wire-length driven placer

16. EXPERIMENTS AND RESULTS • C. Results

17. EXPERIMENTS AND RESULTS

18. EXPERIMENTS AND RESULTS

19. CONCLUSION • A automated tool flow that exploits similarities of a multi-mode circuit and uses Dynamic Circuit Specialization to reduce reconfiguration time.