An automatic tool flow for the combined implementation of multi mode circuits
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An automatic tool flow for the combined implementation of multi-mode circuits. Brahim Al Farisi , Karel Bruneel , Joao M. P. Cardoso and Dirk Stroobandt. DATE’13. OUTLINE. 1. INTRODUCTION 2. RUN-TIME RECONFIGURATION

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An automatic tool flow for the combined implementation of multi mode circuits

An automatic tool flow for the combinedimplementation of multi-mode circuits

Brahim Al Farisi, KarelBruneel, Joao M. P. Cardoso and Dirk Stroobandt

DATE’13


Outline
OUTLINE

  • 1.INTRODUCTION

  • 2. RUN-TIME RECONFIGURATION

  • 3. GENERATING A PARAMETERIZED CONFIGURATION FOR MULTI-MODE CIRCUITS

  • 4. EXPERIMENTS AND RESULTS

  • 5. CONCLUSION


Introduction
INTRODUCTION

  • run-time reconfiguration (RTR)

    • The inherent reconfigurability of SRAM-based FPGAs enables the use of different configurations at different time intervals.

    • Using RTR, global area can be reduced by reusing FPGA resources between circuits.

  • reconfiguration time

    • change between these functions a period of time is needed, to rewrite the configuration memory


Introduction1
INTRODUCTION

  • The conventional way of building RTR systems needs to be rewritten, this often leads to very long reconfiguration times [2].

  • multi-mode circuit

    • the functionality of a limited number of circuits, of which at any given time only one needs to be realised


Run time reconfiguration
RUN-TIME RECONFIGURATION

  • A. Modular Dynamic Reconfiguration[1]

    • When implementing a multi-mode circuit with MDR, every mode will be placed in a separate module.


Run time reconfiguration1
RUN-TIME RECONFIGURATION

  • B. Dynamic Circuit Specialization[3]



Generating a parameterized configuration for multi mode circuits1
GENERATING A PARAMETERIZED CONFIGURATION FOR MULTI-MODE CIRCUITS

  • Merging of several LUT circuits into a Tunable circuit consists of two steps:

    • 1) determine which LUTs will be implemented using the same Tunable LUT


Generating a parameterized configuration for multi mode circuits2
GENERATING A PARAMETERIZED CONFIGURATION FOR MULTI-MODE CIRCUITS

  • 2) the annotation of the connections with the appropriate activation function to generate the Tunable connections.



Generating a parameterized configuration for multi mode circuits4
GENERATING A PARAMETERIZED CONFIGURATION FOR MULTI-MODE CIRCUITS

  • A. Combined placement

    • The conventional placement tool is based on simulated annealing

      • only one LUT is allowed per physical LUT

    • New placement tool to accommodate the simultaneous placement of several LUT circuits

      • LUTs belonging to different modes can be placed on the same physical LUT.


Generating a parameterized configuration for multi mode circuits5
GENERATING A PARAMETERIZED CONFIGURATION FOR MULTI-MODE CIRCUITS

  • B. Optimization options

    • circuit edge matching

      • reduce the number of Tunable connections by placing the LUTs of the different modes in such a way that the number of connections that have the same source and sink is maximized

      • Circuit edge matching [6]only looks at the topology of the Tunable circuit that is formed and does not take into account the placement of the Tunable LUTs.


Generating a parameterized configuration for multi mode circuits6
GENERATING A PARAMETERIZED CONFIGURATION FOR MULTI-MODE CIRCUITS

  • wire-length optimization

    • the cost function used in the wire-length optimization approach uses an estimation of the wire length TRoute will need to route the Tunable circuit.


Experiments and results
EXPERIMENTS AND RESULTS CIRCUITS

  • A. Benchmarks


Experiments and results1
EXPERIMENTS AND RESULTS CIRCUITS

  • B. FPGA architecture

    • The combined placement algorithm was implemented based on our Java version of the VPR (Versatile Place and Route) wire-length driven placer


Experiments and results2
EXPERIMENTS AND RESULTS CIRCUITS

  • C. Results




Conclusion
CONCLUSION CIRCUITS

  • A automated tool flow that exploits similarities of a multi-mode circuit and uses Dynamic Circuit Specialization to reduce reconfiguration time.


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