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درس مدارهای منطقی دانشگاه قم lc-qom.blogfa / مولتی پلکسر Multiplexer) ) و

درس مدارهای منطقی دانشگاه قم http://lc-qom.blogfa.com / مولتی پلکسر Multiplexer) ) و دِ مولتی پلکسر ( Demultiplexer ) تهیه شده توسط حسین امیرخانی مبتنی بر اسلایدهای درس مدارهای منطقی دانشگاه امیرکبیر http://ceit.aut.ac.ir/~szamani/index_files/logic.htm. I. 0. 2:1. Z. mux. I. 1. A.

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درس مدارهای منطقی دانشگاه قم lc-qom.blogfa / مولتی پلکسر Multiplexer) ) و

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  1. درس مدارهای منطقی دانشگاه قم http://lc-qom.blogfa.com/ مولتی پلکسر Multiplexer)) و دِ مولتی پلکسر (Demultiplexer) تهیه شده توسط حسین امیرخانی مبتنی بر اسلایدهای درس مدارهای منطقی دانشگاه امیرکبیر http://ceit.aut.ac.ir/~szamani/index_files/logic.htm

  2. I 0 2:1 Z mux I 1 A I 0 A Z I 1 4:1 Z I 0 I mux 2 I 0 3 1 I 1 A B I 0 I 1 I 2 I 3 8:1 Z I mux 4 I 5 I 6 I 7 A B C Multiplexer • معنی لغوی • تسهیم کردن • چند خبر را روی یک خط فرستادن • مشخصات • 2n data inputs, • n select inputs, • 1 output • Used to connect 2n points to a single point • control signal pattern form binary index of input connected to output

  3. … Multiplexer

  4. I A 0 A I0 2:1 Z mux I 00 01 11 10 1 I1 0 0 1 0 0 A 1 0 1 1 1 I 0 I 1 4:1 Z I I0 mux 2 I 3 A B I 0 I 1 I 2 I 3 8:1 Z I mux 4 I 2n -1 5 In general, Z = S mk Ik I 6 I k=0 7 in minterm shorthand form A B C Boolean Functions Z = A' I0 + A I1 Z = A' B' I0 + A' B I1 + A B' I2 + A B I3 Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 + A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7

  5. Circuit Diagram • 4-to-1 MUX A B I0 I1 I2 I3

  6. I 0 0 4:1 I 1 mux 1 2 I 2 3 S S I 2:1 1 0 0 3 mux I 0 4:1 4 1 S I 1 mux 5 2 I 6 3 S S I 1 0 7 Cascading MUXes (ترکیب مولتی پلکسرها) • Design a MUX (8:1) by smaller MUXes Z B C A پرارزش

  7. Another Implementation پرارزش

  8. Larger Data Lines • What if we want to select m-bit data/words? • Combine MUX blocks in parallel with common select and enable signals

  9. I I I I 0 0 0 0 2:1 2:1 2:1 2:1 Z Z Z Z mux mux mux mux I I I I 1 1 1 1 A A A ? 4-bit data • Example: • Selection between 2 sets of 4-bit inputs x0 x1 x2 z0 x3 z1 z2 y0 z3 y1 y2 y3 A

  10. Application A B C D Multiple input sources: A+C or A+D or B+C or B+D Sa MUX MUX Sb Y X Sum

  11. design Mux by decoder

  12. S 0 I 0 I 1 S 1 Y I 2 I 3 (b) MUX by 3-State Buffers • Three-state logic in place of AND-OR Output of gates can be connected

  13. A B C F A B F 1 0 0 0 0 1 0 0 0 C’ 1 1 0 0 1 0 2 0 1 C’ F 8:1 0 3 0 1 0 1 1 0 0 MUX 0 4 0 1 1 0 1 1 1 0 5 1 0 0 0 1 6 1 0 1 0 1 7 S2 S1 S0 1 1 0 1 A B C 1 1 1 1 General Logic by MUX • Example: F = A' B' C' + A' B C' + A B C' + A B C = A' B' (C') + A' B (C') + A B' (0) + A B (1) C’ C’ 0 1

  14. General Logic by MUX • Any Boolean function of n variables can be implemented using a 2n-to-1 multiplexer. • Any Boolean function of n variables can be implemented using a 2n-1-to-1 multiplexer with only not gates.

  15. Using Smaller MUX • How about implementing a 4-variable function by a 4-to-1 MUX • Anything else is needed?

  16. General Logic • By decoder: • Multiple outputs: • A single decoder, • One more OR for each output • By MUX: • Multiple outputs: • One more MUX for each output, • No need for OR •  Use MUX for few outputs, •  Use decoder for many outputs.

  17. سال 81 مثال سال 82

  18. مثال • سال 83 • سال 80

  19. مثال • سال 84

  20. Standard MSI MUXes • 74x151 • 8:1 MUX

  21. Standard MSI MUXes • 74x157 • 2:1 4-bit MUX

  22. Demultiplexer DEMUX

  23. DEMUX

  24. ABC ABC O0 ABC O1 A S2 ABC 3:8 O2 dec ABC B S1 O3 ABC O4 C S0 ABC O5 ABC O6 O7 Enb Decoder vs. Demux

  25. ABC ABC O0 ABC O1 A S2 ABC 3:8 O2 dec ABC B S1 O3 ABC O4 C S0 ABC O5 ABC O6 O7 Enb Decoder vs. Demux

  26. سؤالات آزمون کارشناسی ارشد

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