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Dezső Sima 20 1 2 December. Platforms I. (Ver. 1 . 5 ).  Sima Dezső, 20 11. Contents. 1. Introduction to platforms. 2. Main components of platforms. 3 . Platform architectures. 4 . Memory subsystem design considerations. 5. References. 1. Introduction to platforms.

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Dezs sima 20 1 2 december

Dezső Sima

2012 December

Platforms I.

(Ver. 1.5)

 SimaDezső, 2011


Dezs sima 20 1 2 december

Contents

1. Introduction to platforms

2. Main components of platforms

3. Platform architectures

4. Memory subsystem design considerations

5. References


Dezs sima 20 1 2 december

1. Introduction to platforms

1.1. The notion of platform

1.2. Description of particular platforms

1.3. Representation forms of platforms

1.4. Compatibility of platform components


Dezs sima 20 1 2 december

1.1. The notion of platform


Dezs sima 20 1 2 december

1.1The notion of platform (1)

1.1 The notion of platform

The notion platform is widely used in different segments of the IT industry e.g. by

IC manufacturers, system providers or even by software suppliers with different interpretations.

Here we are focusing on the platform concept as used typically by system providers.


Dezs sima 20 1 2 december

1.1The notion of platform (2)

Modular (unified) system design and the notion platform

Modular system design means that the system architecture is partitioned to a few

standard components (modules), such as the processor, memory control hub (MCH),

I/O control hub (ICH) that are interconnected by specified (standard) interconnections.

Core2 Duo

Core 2 Extreme

(2C)

FSB: 1066/800/533 MT/s speed

FSB

Two memory channels

DDR2-800/666/533

Two DIMMs per channel

965 Series

MCH

ME

C-link

DMI

ICH8

Figure: Intel’s Core 2 Duo (and Core 2 Extreme (the highest speed model) aimed

DT platform (the Bridge Creek platform)


Dezs sima 20 1 2 december

1.1The notion of platform (3)

Modular system design became part of scientific research at the end of the 1990s, see e.g. [4].

Remark

The need for a modular system design, called platform design, arose in the PC industry

when PCI-based system designs were substituted by port based system designs,

about 1998-1999 .


1 1 the notion of platform 4

1.1The notion of platform (4)

Pentium II/

Pentium II/

Pentium III

Pentium III

Pentium III

Processor bus

Processor bus

Main Memory

System

System

Main Memory

AGP

controller

AGP

(SDRAM)

controller

(EDO/SDRAM)

2xIDE/

Hub interface

ATA 33/66/100

LPC

PCI bus

Peripheral

Super I/O (KBD, MS, etc.)

controller

AC'97

2xIDE/ATA33/66

2x/4x USB

(Legacy and/or

PCI device

adapter

slow devices)

Peripheral

controller

PCI bus

2xUSB

PCI device

PCI to ISA

adapter

bridge

ISA bus

ISA bus

ISA device

adapter

Legacy

devices

ISA device

adapter

Late PCI-based system architecture(~ 1998)

(used typically with Pentium II/III

(built around Intel’s 440xx chipset)

Early port-based system architecture(~ 1999)

(used first with Pentium III

(built around Intel’s 810 chipset)


Dezs sima 20 1 2 december

1.1The notion of platform (5)

Main goals of modular system level design

  • to reduce the complexity of designing complex systems by partitioning it to modules,

  • to have stable interfaces (at least for a few number of years) interconnecting the modules

  • in this way

  • to minimize design rework while upgrading a given system design, like moving from

  • one processor generation to the next and thus

  • to shorten the time to market.

Co-design of platform components

Platform components are typically co-designed, announced and delivered as a set.


Dezs sima 20 1 2 december

1.1The notion of platform (6)

The notion of platforms

System providers however, may use the notion platform either in a more general or a more specific sense.

Interpretation of the notion platform

Interpretation in a

more general sense

Interpretation in a

more specific sense

A modular system design targeting a given

application area,

used as terms like DT or MP platforms.

A particular modular system architecture,

developed for a given application area,

such as a given DT or MP platform, like

Intel’s Sandy Bridge Based Sugar Bay DT platform or

AMD’s Phenom II X! based Dragon platform (2008)

for gamers (2009)


1 1 the notion of platform 7

1.1The notion of platform (7)

Benefits of the platform concept for computer manufacturers

  • With the platform concept in mind manufacturers, like Intel or AMD will plan, design

  • and market all key components of a platforms, such as the processor or the processors

  • and the related chipset as an integrated entity [5].

  • This is beneficial for the manufacturers since it motivates OEMs as system providers,

  • to buy all key parts of a computer system from the same manufacturer.


1 1 the notion of platform 8

1.1The notion of platform (8)

Benefits of the platform concept for customers

The platform concept is beneficial for the customers as well since an integrated “backbone”

of a system architecture promises a more reliable and more cost effective system.


1 1 the notion of platform 9

1.1The notion of platform (9)

Interpretation the notion platform in a more specific sense

In a more specific sensethe notion platform refers to a particular modular system architecture,

that is developed for a given application area, such as a DT, DP or MP platform.

In this sense the notion platform is interpreted as a standardized backboneof a

system architecture developed for a given application area that is built up typically of

  • the processor or processors,

  • the chipset,

  • the memorysubsystem (MSS) that is attached by a specific memory interface

  • in some cases, such as in mobile or business oriented DT platforms also the

  • networking component [7] as well

  • the buses interconnecting the above components of the platform..

Basic components of a platform

The memory

subsystem

(LAN

controller)

Chipset

Buses

interconnecting

the preceding

basic components

Processor or

processors

Subsequently, we will focus on the interpretation of the notion platform in this latter sense.


Dezs sima 20 1 2 december

1.1The notion of platform (10)

Example 1: Intel’s Core 2 aimed home user DT platform (Bridge Creek) [3]

Platform

1066 MT/s

Display

card

2 DIMMs/channel

2 DIMMs/channel

C-link


1 1 the notion of platform 11

1.1The notion of platform (11)

Example 2: Intel’s Nehalem-EX aimed Boxboro-EX MP server platform, assuming 1 IOH

Platform

Xeon 7500

(Nehalem-EX)

(Becton) 8C

Xeon 7-4800

(Westmere-EX) 10C

/

SMB

SMB

SMB

SMB

Nehalem-EX 8C

Westmere-EX 10C

Nehalem-EX 8C

Westmere-EX 10C

QPI

SMB

SMB

SMB

SMB

QPI

QPI

QPI

QPI

SMB

SMB

Nehalem-EX 8C

Westmere-EX 10C

Nehalem-EX 8C

Westmere-EX 10C

SMB

SMB

SMB

QPI

SMB

SMB

SMB

QPI

QPI

2x4 SMI

channels

2x4 SMI

channels

7500 IOH

DDR3-1067

DDR3-1067

ME

ESI

SMI: Serial link between

the processors and SMBs

SMB: Scalable Memory Buffer

Parallel/serial conversion

ICH10

Interfaces connecting platform

components

ME: Management Engine


1 1 the notion of platform 12

1.1The notion of platform (12)

The structure of a platform is termed as its architecture (or topology).

It describes the basic components and their interconnections and will be discussed in Section 3.


1 1 the notion of platform 13

1.1The notion of platform (13)

Historical remarks

System providers began using the notion “platform” about 2000, like

  • Philips’ Nexperia digital video platform (1999),

  • Texas Intruments (TI) OMAP platform for SOCs (2002),

  • Intel’s first generation mobile oriented Centrino platform for laptops, designated as the

  • Carmel platform (3/2003).

Intel contributed significantly for spreading the notion platform when based on the success

of their Centrino platform they introduced this concept also for their desktops [5] and servers

[6], [7] in 2004.


1 1 the notion of platform 14

1.1The notion of platform (14)

Intel’s early server and workstation roadmap from Aug. 2004 [6]

Note

  • This roadmap already makes use of the notion platform without revealing platform names.

  • b) In 2004 Intel made a transition from 32 bit systems to 64 bit systems.


1 1 the notion of platform 15

1.1The notion of platform (15)

Intel’s multicore platform roadmap announced at the IDF Spring 2005 [8]

Note

This roadmap includes also the particular platform designations for desktops, UP servers etc.


Dezs sima 20 1 2 december

1.2. Description of a particular platform


1 2 description of a particular platform 1

1.2 Description of a particular platform (1)

Description of a particular platform

Description of a particular platform

Detailing the

platform

architecture

Example: The Tylersburg DT platform

(2008)

Processor

MCH

ICH


1 2 description of a particular platform 2

1.2 Description of a particular platform (2)

Detailing the platform architecture includes the specification architecture (topology) of the

processor-, the memory- and the I/O subsystems (to be discussed in Section 3).

Example: The Tylersburg DT platform

(2008)

Processor

MCH

ICH

It is concerned with issues, such as whether the processors of an MP server are connected

to the MCH via an FSB or otherwise, or whether the memory is attached to the

system architecture through the MCH or through the processors etc.).


1 2 description of a particular platform 3

1.2 Description of a particular platform (3)

Description of a particular platform

Description of a particular platform

Identification of the

platform components

Detailing the

platform

architecture

Example: The Tylersburg DT platform

(2008)

1. gen. Nehalem (4C)/Westmere-EP (6C)

Processor

X58 IOH

MCH

ICH10

ICH


1 2 description of a particular platform 4

1.2 Description of a particular platform (4)

Description of a particular platform

Description of a particular platform

Identification of the

platform components

Detailing the

platform

architecture

Specification of the

interfaces

interconnecting

the platform components

Example: The Tylersburg DT platform

(2008)

1. gen. Nehalem (4C)/Westmere-EP (6C)

1. gen. Nehalem (4C)/Westmere-EP (6C)

Processor

QPI

X58 IOH

X58 IOH

MCH

DMI

ICH10

ICH10

ICH


1 2 description of a particular platform 5

1.2 Description of a particular platform (5)

Remark

The specification of a platform will be completed by thedatasheets of the related platform

components.


1 2 description of a particular platform 6

1.2 Description of a particular platform (6)

Dependence of the platform architecture on the platform category

Platforms may be classified according to the target area of application, such as

Platforms

Desktop (DT)

platforms

Dual processor (DP) platforms

Mobile

platforms

Quad processor (MP) platforms

Of course, beyond the above categories also further processor categories and related platforms

exist, such as embedded processors and related platforms.

In conformity with different platform categories also different platform architectures arise,

as indicated below.

Platform architecture

Architecture of

DT platforms

Architecture of

DP platforms

Architecture of

mobile platforms

Architecture of

MP platforms

In these slides platform architectures will be discussed in Section 3, nevertheless restricted only for DT, DP and MP platforms.


Dezs sima 20 1 2 december

1.3. Representation forms of platforms


1 3 representation forms of platforms 1

1.3 Representation forms of platforms (1)

1.3 Representation forms of platforms

  • Thumbnail representation

  • Roadmap like representation (an arbitrarily chosen representation form in these slides)

  • Block diagram of a platform.


1 3 representation forms of platforms 3

1.3 Representation forms of platforms (3)

a) Thumbnail representation

It is a concise representation of a particular platform.

In particular, the thumbnail representation

  • reveals the platform architecture,

  • identifies the basic components of a platform, such as the processor or processors, the chipset,

  • in some cases (e.g. in mobile platforms) also the Gigabit Ethernet controller,

  • and specifies the interconnection links (buses) between the platform components.

Example

Core2 Duo

Core 2 Extreme

(2C)

FSB: 1066/800/566 MT/s speed

FSB

Two DDR2 channels

965 Series

MCH

DDR2-800/666/566

Two DIMMs per channel

ME

C-link

DMI

ICH8

Intel’s Core 2 Duo aimed home user oriented platform (The bridge Creek platform)


1 3 representation forms of platforms 4

1.3 Representation forms of platforms (4)

DT platform

DP cores

MCH

ICH

6/2006

b) Roadmap like representation

Bridge Creek

This kind of representation

7/2006

  • indicates a few additional data of the processor and the chipset,

  • (like data of the die, the cache system or the memory)

  • reveals the dates of the introduction of platform components, and

  • identifies compatibility ranges of processors or chipsets

  • in platforms by encircling compatible components,

  • but lacks the graphical representation of the platform.

E6xxx/E4xxx

X6800

(Conroe: E6xxx/X6800)1

Allendale: E4xxx)1

Core 2 Extreme 2C

Core 2 Duo 2C

65 nm

Conroe: 291 mtrs/143 mm2

Allendale: 167 mtrs/111 mm2

Conroe: 4 MB/Allendale 2 MB L2

X6800/E6xxx: 1066 MT/s

E4xxx: 800MT/s

LGA775

6/2006

965 Series

(Broadwater)

FSB

1066/800/566 MT/s

2 DDR2 channels

DDR2-800/666/533

4 ranks/channel

8 GB max.

6/2006

ICH8

1The Allendale is a later stepping (Steppings L2/M0) of the Core 2 (Steppings B2/G0),

that provided typically only 2 MB L2 and appeared 1/2007.

Core 2-aimed (65 nm)


1 3 representation forms of platforms 5

1.3 Representation forms of platforms (5)

6/2006

Bridge Creek

DT platform

7/2006

Core 2 Duo (2C)

Core 2 Extr. (2C)

DTcore

Core 2 Duo (2C):E6xxx/E4xxx

Core 2 Extreme (2C): X6800

E6xxx/X68001: Conroe

E4xxx)1: Allendale

65 nm

Conroe: 291 mtrs/143 mm2

Allendale: 167 mtrs/111 mm2

Conroe: 4 MB/Allendale 2 MB L2

X6800/E6xxx: 1066 MT/s

E4xxx: 800MT/s

LGA775

6/2006

965 Series

MCH

(Broadwater)

FSB

1066/800/566 MT/s

2 DDR2 channels

DDR2-800/666/533

4 ranks/channel

8 GB max.

6/2006

ICH8

ICH

Core 2-aimed (65 nm)

Example for stating the compatibility range of a platform

The Core 2 Duo aimed DT platformthat targets

home users (designated as the Bridge Creek platform).

Core2 Duo

Core 2 Extreme

(2C)

FSB: 1066/800/566 MT/s speed

FSB

Two DDR2 channels

965 Series

MCH

DDR2-800/666/566

Two DIMMs per channel

ME

C-link

DMI

ICH8

Beyond the target processor this platform may be used also with

  • the previous Pentium D/EE and Pentium 4 6x0/6x1/EE and

  • the subsequent Core 2 Quad lines of processors,

as shown in the next slides.

1The Allendale is a later stepping (Steppings L2/M0) of the Core 2 (Steppings B2/G0),

that provided typically only 2 MB L2 and appeared 1/2007.


1 3 representation forms of platforms 51

1.3 Representation forms of platforms (5)

6/2006

Bridge Creek

DT platform

7/2006

Core 2 Duo (2C)

Core 2 Extr. (2C)

DTcore

Core 2 Duo (2C):E6xxx/E4xxx

Core 2 Extreme (2C): X6800

E6xxx/X68001: Conroe

E4xxx)1: Allendale

65 nm

Conroe: 291 mtrs/143 mm2

Allendale: 167 mtrs/111 mm2

Conroe: 4 MB/Allendale 2 MB L2

X6800/E6xxx: 1066 MT/s

E4xxx: 800MT/s

LGA775

6/2006

965 Series

MCH

(Broadwater)

FSB

1066/800/566 MT/s

2 DDR2 channels

DDR2-800/666/533

4 ranks/channel

8 GB max.

6/2006

ICH8

ICH

Core 2-aimed (65 nm)

Example for stating the compatibility range of a platform

The Core 2 Duo aimed DT platformthat targets

home users (designated as the Bridge Creek platform).

Core2 Duo

Core 2 Extreme

(2C)

FSB: 1066/800/566 MT/s speed

FSB

Two DDR2 channels

965 Series

MCH

DDR2-800/666/566

Two DIMMs per channel

ME

C-link

DMI

ICH8

Beyond the target processor this platform may be used also with

  • the previous Pentium D/EE and Pentium 4 6x0/6x1/EE and

  • the subsequent Core 2 Quad lines of processors,

as shown in the next slides.

1The Allendale is a later stepping (Steppings L2/M0) of the Core 2 (Steppings B2/G0),

that provided typically only 2 MB L2 and appeared 1/2007.


1 3 representation forms of platforms 6

1.3 Representation forms of platforms (6)

6/2006

Support of Pentium 4/D/EE processors

Bridge Creek

5/2005

2/2005

1/2006

7/2006

Pentium D/EE

8xx1

Pentium 4

6x0/6x1/EE

Pentium D/EE

9xx2,3

Core 2 Duo (2C)

Core 2 Extr. (2C)

DTcores

(Smithfield) 2x1C

(Presler) 2x1C

Core 2 Duo (2C):E6xxx/E4xxx

Core 2 Extreme (2C): X6800

E6xxx/X68001: Conroe

E4xxx)1: Allendale

(Prescott-2M) 1C

65 nm

Conroe: 291 mtrs/143 mm2

Allendale: 167 mtrs/111 mm2

Conroe: 4 MB/Allendale 2 MB L2

X6800/E6xxx: 1066 MT/s

E4xxx: 800MT/s

LGA775

90 nm

169 mtrs

135 mm2

2 MB L2

800 MT/s

Two-way multithreading

LGA775

90 nm

2x115 mtrs

2x103 mm2

2x1 MB L2

800/533 MT/s

No multithreading

LGA775

65 nm

2x188 mtrs

2x81 mm2

2x2 MB L2

1066/800 MT/s

No multithreading

LGA775

6/2006

965 Series

MCH

(Broadwater)

FSB

1066/800/566 MT/s

2 DDR2 channels

DDR2-800/666/533

4 ranks/channel

8 GB max.

1Pentium EE 840 supports only 800 MT/s

2Pentium D 9xx support only 800 MT/s

3Pentium EE 955/965 supports only 1066 MT/s

6/2006

ICH8

ICH

Supports also

Pentium D/EE processors/90/65 nm

Supports also

Pentium 4 6x0/6x1/EE processors/90nm

Core 2-aimed (65 nm)


1 3 representation forms of platforms 7

1.3 Representation forms of platforms (7)

6/2006

Support of Core 2 Quad processors)

Bridge Creek

DT platform

11/2006

7/2006

Core 2 Duo (2C)

Core 2 Extr. (2C)

Core 2 Quad (2x2C)

DTcore

Core 2 Duo (2C):E6xxx/E4xxx

Core 2 Extreme (2C): X6800

E6xxx/X68001: Conroe

E4xxx)1: Allendale

Core 2 Quad (2x2C): Q6xxx

Q6xxx: Kentsfield

65 nm

Conroe: 291 mtrs/143 mm2

Allendale: 167 mtrs/111 mm2

Conroe: 4 MB/Allendale 2 MB L2

X6800/E6xxx: 1066 MT/s

E4xxx: 800MT/s

LGA775

65 nm

2x291 mtrs/2x143 mm2

2*4 MB L2

1066 MT/s

LGA775

6/2006

965 Series

MCH

(Broadwater)

FSB

1066/800/566 MT/s

2 DDR2 channels

DDR2-800/666/533

4 ranks/channel

8 GB max.

6/2006

ICH8

ICH

Supports also

Core 2 Quad processors/65 nm

Core 2-aimed (65 nm)


Dezs sima 20 1 2 december

1.3 Representation forms of platforms (8)

c) Block diagram of a platform

Example: The Core 2 aimed home user DT platform (Bridge Creek)

(without an integrated display controller) [3]

1066 MT/s

Display

card

2 DIMMs/channel

2 DIMMs/channel

C-link


Dezs sima 20 1 2 december

1.4. Compatibility of platform components


1 4 compatibility of platform components 1

1.4Compatibility of platform components (1)

1.4 Compatibility of platform components

One of the goals of platform based designs is to use stabilized interfaces (at least for a while)

to minimize or eliminate design rework while moving from one processor generation to the

next [2].

Consequently, assuming platform based designs,platform components, such as processors

or chipsets of a given lineare typically compatible with their previous or subsequent generations

as long as the same interfaces are used and interface parameters (such FSB speed) or

other implementation requirements (either from side of the components to be substituted or

the substituting components) do not restrict this.


1 4 compatibility of platform components 2

1.4Compatibility of platform components (2)

Limits of compatibility

In the discussed DT platform the target processor is the Core 2, that is connected to the MCH byan FSB with 1066/800/533 MT/s.

The target processor of the platform however, can be substituted

  • either by processors of three previous generations or

  • processors of the subsequent generation (Core 2 Quad)

since all these processors have FSBs of 533/800/1066 MT/s, as shown before.

Core2 Duo

Core 2 Extreme

(2C)

FSB: 1066/800/533 MT/s

FSB

Two memory channels

DDR2-800/666/533

Two DIMMs per channel

965 Series

MCH

ME

C-link

DMI

ICH8

Nevertheless, The highest performance level Core 2 Quad, termed as the Core 2 Extreme Quad,

provided already an increased FSB speed of 1333 MT/s and therefore was not more supported

by the Core 2 aimed platform considered.


Dezs sima 20 1 2 december

2. Basic components of platforms

2.1. Processors

2.2. The memory subsystem

2.3. Buses interconnecting platform components


1 1 the notion of platform 6

1.1The notion of platform (6)

Basic components of platforms - Overview

As already discussed in Section 1. the notion platform is interpreted as a standardized

backboneof a system architecture developed for a given application area that is built up

typically of

  • the processor or processors,

  • the chipset,

  • in some cases, such as in mobile or business oriented DT platforms also the

  • networking component [7],

  • the buses interconnecting the above components of the platform as well as

  • the memorysubsystem (MSS) that is attached by a specific memory interface..

Basic components of a platform

The memory

subsystem

(LAN

controller)

Chipset

Buses

interconnecting

the preceding

basic components

Processor or

processors

Subsequently, we will discuss the following three basic components of platforms:

  • Processors (Section 2.1)

  • Buses interconnecting platform components (excluding memory buses) (Section 2.2) and

  • The memory subsystem (Section 2.2).


Dezs sima 20 1 2 december

2.1. Processors


2 1 processors 1

2.1Processors (1)

Intel’s Tick-Tock model

Key microarchitectural features

TICKTOCK

2 YEARS

Pentium 4 /Willamette

New microarch.

11/2000

180nm

TICKTOCK

2 YEARS

01/2002

Adv. microarch., hyperthreading

130nm

Pentium 4 /Northwood

TICKTOCK

Adv. microarch., hyperthreading,

64-bit

02/2004

Pentium 4 /Prescott

2 YEARS

90nm

TICK Pentium 4 / Cedar Mill

01/2006

2 YEARS

65nm

New microarch., 4-wide core,

128-bit SIMD, no hyperthreading

TOCKCore 2

07/2006

TICK PENRYN Family

11/2007

2 YEARS

45nm

New microarch., hyperthreading,

(inclusive) L3, integrated MC, QPI

TOCKNEHALEM

11/2008

TICKWESTMERE

01/2010

2 YEARS

32nm

New microarch. hyperthreading,

256-bit AVX, integr. GPU, ring bus,

TOCKSANDY BRIDGE

01/2011

TICKIVY BRIDGE

04/2012

2 YEARS

22nm

TOCK HASWELL

Figure 2.1: Overview of Intel’s Tick-Tock model (based on [17])


Dezs sima 20 1 2 december

2.1Processors (2)

Basic architectures and their related shrinks

Considered from the Pentium 4 Prescott (the third core of Pentium 4) on


Dezs sima 20 1 2 december

2.1Processors (4)

In 2003 Intel shifted the focus of their processor development from the performance goal

to the aspect of performance per watt, as stated in a slide from 4/2006, see below.

Figure 2.2: Intel’s plan to develop their manufacturing technology and processor lines

revealed at a shareholder’s meeting back in 4/2006 [18]


Dezs sima 20 1 2 december

2.1Processors (5)

Table 2.1: Intel’s Core 2 based and subsequent multicore DT processor lines


Dezs sima 20 1 2 december

2.1Processors (6)

Table 2.2: Overview of Intel’s multicore DP server processors


Dezs sima 20 1 2 december

2.1Processors (7)

Table 2.2: Overview of Intel’s multicore MP server processors


Dezs sima 20 1 2 december

2.2. The memory subsystem

2.2.1. Key parameters of the memory subsystem

2.2.2. Main attributes of the memory technology used

2.2.2.1. Overview: Main attributes of the memory

technology used

2.2.2.2. Memory type

2.2.2.2. Speed grades

2.2.2.4. DIMM density

2.2.2.5. Use of ECC support

2.2.2.6. Use of registering


2 2 1 key performance parameters of the memory subsystem 1

2.2.1 Key performance parameters of the memory subsystem (1)

2.2.1 Key performance parameters of the memory subsystem

This issue will be discussed in Section 4.


2 2 2 main attributes of the memory technology used

2.2.2 Main attributes of the memory technology used

2.2.2 Main attributes of the memory technology used

2.2.2.1 Overview: Main attributes of the memory technology used

Main attributes of the memory technology used

Use of

ECC support

Use of

registering

Memory type

Speed grade

DIMM density

2.2.2.6

2.2.2.2

2.2.2.5

2.2.2.4

Section

2.2.2.2


2 2 2 2 memory type 1

2.2.2.2 Memory type (1)

DRAMs for general use

DRAMs with parallel bus connection

DRAMs with serial bus connection

Commodity DRAMs

Synchronous DRAMs

Asynchronous DRAMs

FP

(~1974)

XDR

(2006)1

DRDRAM

(1999)

DRAM

(1970)

SDRAM

(1996)

DDR

(2000)

DDR2

(2004)

DDR3

(2007)

FB-DIMM

(2006)

FPM

(1983)

EDO

(1995)

Year

of intro.

Challenging DRAM types

Main stream DRAM types

1 Used in the Cell BE and the PlayStation 3, but not yet in desktops or servers

2.2.2.2 Memory type

a) Overview: Main DRAM types


2 2 2 2 memory type 2

2.2.2.2 Memory type (2)

b) Synchronous DRAMs (SDRAM, DDR, DDR2, DDR3)


Dezs sima 20 1 2 december

2.2.2.2 Memory type (3)

SDRAM to DDR3 DIMMs

SDRAM

168-pin

DDR

184-pin

DDR2

240- pin

DDR3

240-pin

All these DIMM modules are 8-byte wide


2 2 2 2 memory type 4

2.2.2.2 Memory type (4)

Principle of operation of synchronous DRAMs (SDRAM to DDR3 memory chips)

DRAM device

Memory Cell

Array

I/O

Buffers

Memory

controller

(MC)

fCell

fCK

Sources/sinks data

to/from the I/O buffers

Receives/transmit data

to/from the MC

Data transmission

  • on the rising edge

  • of the strobe (CK) for SDRAMs or

  • on both edges of the strobe (DQS)

  • for DDR/DDR2/DDR3.

  • at a rate of fCell

  • at a width of FW

  • at a rate of fCK (SDRAM) or

  • 2 x fclock (DDR to DDR3)


2 2 2 2 memory type 5

2.2.2.2 Memory type (5)

Sourcing/sinking data by the memory cell array

The memory cell arraysources/sinksdata to/from the I/O buffers

  • at a rate of fCell, where fCellis the clock frequency of the memory cell aray,

  • at a data width of FW, where FW is the fetch width of the memory cell array.

The core clock frequency of the memory cell array (fcell)

  • fCell is 100 to 200 MHz

  • It stands in a given ratio with the clock frequency of the memory device (fCK) as follows:

Raising fCell from 100 MHz to 200 MHz characterizes the evolution of each memory technology

  • When a new memory technology (e.g. DDR2 or DDR3) appears fCore is initially 100 MHz,

  • .this sets the initial speed grade of fCK accordingly (e.g. to 400 MT/s for DDR2 or

  • to 800 MT/s for DDR3).

  • As memory technology evolves fCore will be raised from 100 MHz to 133, 167 and to 200 MHz.

  • Along with fCore fCK and the final speed grade will also be raised.


2 2 2 2 memory type 6

2.2.2.2 Memory type (6)

The fetch width (FW) of the memory cell array

It specifies how many times more bits the cell array fetches per column cycle

then the data width of the device (xn).

E.g. a 4-bit wide DRAM device (x4 DRAM chip) with a fetch width of 4 (actually a DDR2 DRAM) fetches 4 × 4 that is 16 bits from the memory cell array in everyfCellcycle.

The fetch width(FW)of the memory cell array of synchronous DRAMs is as follows:


2 2 2 2 memory type 7

2.2.2.2 Memory type (7)

Transferring data between the I/O Buffers and the Memory Controller

Data transmission between the I/O buffers and the Memory Controller is clocked by

a frequency of fCK.

Data transmission occurs

  • for SDRAMsat the rising edge of the strobe signal (CK)

  • for DDR/DDR2/DDR3at both edges of the strobe signal (DQS),

  • designated as the Double Data Rate transfer)

The final transfer rate (speed grade) results in

  • fCK for SDRAMs

  • 2 x fCK for DDR/DDR2/DDR3

Accordingly, typical speed grade ranges cover

  • 100 to 200 MT/s for SDRAM devices,

  • 200 to 400 MT/s for DDR devices,

  • 400 to 800 MT/s for DDR2 devices and

  • 800 to 1600 MT/s for DDR3 devices.


Dezs sima 20 1 2 december

Clock frequency (fCK)100 MHz

DRAM core frequency100 MHz

Clock (CK)

100 MHz

E.g.

Memory CellArray

I/OBuffers

fCell

fCK

SDRAM

Data transfer on the rising edges of CK

over the data lines (DQ0 - DQn-1)

100 MT/s

SDRAM-100

n bits

n bits

Data Strobe (DQS)

100 MHz

DRAM core clock100 MHz

Clock (CK/CK#)100 MHz

E.g.

Memory CellArray

I/OBuffers

DDRSDRAM

fCell

fCK

Data transfer on both edges of DQS

over the data lines (DQ0 - DQn-1)

200 MT/s

DDR-200

n bits

2xn bits

DRAM core clock100 MHz

Data Strobe (DQS)

200 MHz

Clock (CK/CK#)200 MHz

E.g.

Memory CellArray

I/OBuffers

fCell

DDR2SDRAM

2 x fCK

Data transfer on both edges of DQS

over the data lines (DQ0 - DQn-1)

400 MT/s

DDR2-400

n bits

4xn bits

Data Strobe (DQS)

400 MHz

DRAM core clock100 MHz

Clock (CK/CK#)400 MHz

E.g.

fCell

Memory CellArray

I/OBuffers

DDR3SDRAM

2 x fCK

Data transfer on both edges of DQS

over the data lines (DQ0 - DQn-1)

800 MT/s

DDR3-800

n bits

8xn bits


2 2 2 2 memory type 9

2.2.2.2 Memory type (9)

The main technique to increase memory speed

Relation between voltage swings and rise/fall times of signals

Q = Cin x V = I x t tR~ Cin x V/I

Q: Charge on the input capacitance of the line (Cin)

Cin: Input capacitance of the line

V: Voltage

I: Current strength of the driver

tR: Rise time

shorter signal rise/fall times

higher speed grades

Smaller

voltage

swings

but lower voltage budget

higher requirements for signal integrity

Memory type

Voltage/Voltage swing

SDRAM

DDR

DDR2

DDR3

3.3 V

2.5 V

1.8 V

1.5 V


2 2 2 2 memory type 10

2.2.2.2 Memory type (10)

Single ended

(TTL, LVTTL)

Voltage ref.

(RSL, SSTL)

Signaling of data lines

Differential

(DRSL, LVDS)

Signaling of command, control and adress lines

Differential

(DRSL, LVDS)

Single ended

(TTL, LVTTL)

Voltage ref.

(RSL, SSTL)

FPM

EDO

SDRAM

DDR

DDR2

DDR3

RDRAM

XDR

XDR2

FBDIMM

Figure 2.7: Signaling alternatives of buses used with memories


2 2 2 2 memory type 11

2.2.2.2 Memory type (11)

Key features of synchronous DRAM devices (SDRAM to DDR3)

Table 2.4: Key features of synchronous DRAM devices


2 2 2 2 memory type 12

2.2.2.2 Memory type (12)

Approximate appearance dates and speed grades of DDR DRAMs

as well as the bandwidth provided by a dual channel memory subsystem

Bandwidth1

1 Bandwidth of a dual channel memory subsystem [12]


2 2 2 2 memory type 13

2.2.2.2 Memory type (13)

Green and ultra-low power memories

They represents the latest achievements of the DRAM memory technology

Green memories: lower dissipation memories

Ultra-low-power DDR3 memories: Use of 1.35 V supply voltage instead of 1.50 V

to reduce dissipation


2 2 2 2 memory type 14

2.2.2.2 Memory type (14)

Green and ultra-low power memories- Examples[13]


2 2 2 2 memory type 15

2.2.2.2 Memory type (15)

c) FB-DIMMs

DRAMs for general use

DRAMs with parallel bus connection

DRAMs with serial bus connection

Synchronous DRAMs

Asynchronous DRAMs

FP

(~1974)

XDR

(2006)1

DRDRAM

(1999)

DRAM

(1970)

SDRAM

(1996)

DDR

(2000)

DDR2

(2004)

DDR3

(2007)

FB-DIMM

(2006)

FPM

(1983)

EDO

(1995)

Year

of intro.

Challenging DRAM types

Main stream DRAM types

1 Used in the Cell BE and the PlayStation 3, but not yet in desktops or servers


2 2 2 2 memory type 16

2.2.2.2 Memory type (16)

Principle of operation

  • Introduce packed based serial transmission (like in the PCI-E, SATA, SAS buses)

  • Introduce full buffering (registered DIMMs buffer only addresses)

  • CRC error checking (cyclic redundancy check)


2 2 2 2 memory type 17

2.2.2.2 Memory type (17)

The architecture of FB-DIMM memories[19]


2 2 2 2 memory type 18

2.2.2.2 Memory type (18)

Figure 2.8: Maximum supported FB-DIMM configuration [20]

(6 channels/8 DIMMs)


2 2 2 2 memory type 19

2.2.2.2 Memory type (19)

Implementation details (1)

  • Serial (differential) transmission between the North Bridge and the DIMMs

  • (each bit needs a pair of wires)

  • Number of seral links

    • 14 read lanes (2 wires each)

    • 10 write lanes (2 wires each)

  • Clocked at 6 x data rateof the DDR2

  • e.g. for a DDR-667 DRAM the clock rate is: 6 x 667 MHz = 4 GHz

  • Every 12 cycles (that is every two memory cycles) constitute a packet.

  • Read packets (frames, bursts): 168 bits (12 x 14 bits)

  • 144 data bits

  • (equals the number of data bits produced by a 72 bit wide DDR2 module

  • (64 data bits + 8 ECC bits) in two memory cycles)

  • 24 CRC bits.

  • Write packets (frames, bursts): 120 bits (12 x 10 bits)

  • 98 payload bits

  • 22 CRC bits.


2 2 2 2 memory type 20

2.2.2.2 Memory type (20)

Implementation details (2)

  • 98 payload bits.

    • 2 frame type bits,

    • 24 bits of command,

    • 72 bits for data and commands, according to the frame type,

    • e.g. 72 bits of data, 36 bits of data + one command or two commands.

Commands

  • all commands include a 3-bit FB-DIMM module address to select one of 8 modules.


2 2 2 2 memory type 22

2.2.2.2 Memory type (22)

FB-DIMM data puffer

(Advanced Memory Buffer, AMB)

Manages the read/write operations

of the module

Source: PC stats

FB-DIMM-4300 (DDR2-533 SDRAM); Clock Speed: 133MHz, Data Rate: 532MHz, Through-put 4300MB/sFB-DIMM-5300 (DDR2-667 SDRAM); Clock Speed: 167MHz, Data Rate: 667MHz, Through-put 5300MB/sFB-DIMM-6400 (DDR2-800 SDRAM); Clock Speed: 200MHz, Data Rate: 800MHz, Through-put 6400MB/s

Figure 2.9: Different implementations of FB-DIMMs


Dezs sima 20 1 2 december

2.2.2.2 Memory type (23)

Figure 2.10: Block diagram of the AMB [21]

(There are two Command/Address buses (C/A) to limit loads of 9 to 36 DRAMs)


2 2 2 2 memory type 24

2.2.2.2 Memory type (24)

Necessary routing to connect the north bridge to the DIMM socket

b) In case of an FB-DIMM

(69 pins)

a) In case of a DDR2 DIMM

(240 pins)

A 2-layer PCB is needed

(but a 3. layer is used for power lines)

A 3-layer PCB is needed

Figure 2.11: PCB routing [19]


2 2 2 2 memory type 25

2.2.2.2 Memory type (25)

Assessing benefits and drawbacks of FB-DIMM memories

(as compared to DDR2/3 memories)

Benefits of FB-DIMMs

  • more memory channels (up to 6)

higher memory size and bandwidth

  • more DIMM modules (up to 8) per channel

higher memory size (6x8=48 DIMM size)

asuming 8 GB/DIMM

up to 512 GB

  • same bandwidth figures as the parts based on (DDR2)

Drawbacks of FB-DIMMs

  • higher latency

  • higher dissipation

(Typical dissipation figures: DDR2: about 5 W

AMB: about 5 W

FB-DIMM with DDR2: about 10 W)

  • higher cost


2 2 2 2 memory type 26

2.2.2.2 Memory type (26)

Latency [22]

  • Due to their additional serialization tasks and daisy-chained nature FB-DIMMs have

  • about 15 % higher overall average latency than DDR2 memories.

Production

The production of FB-DIMMs stopped with DDR2-800 modules, no DDR3 modules came to the

market due to the drawbacks of the technology.


2 2 2 2 speed grades 1

2.2.2.2 Speed grades (1)

2.2.2.2 Speed grades

Overview of the speed grades of DDR DRAMs

Bandwidth1

1 Bandwidth of a dual channel memory subsystem [12]


Dezs sima 20 1 2 december

2.2.2.2 Speed grades (2)

Remark

Speed grades of FSBs and DRAMs were defined at the time when the base clock frequency

of the FSBs was 133 MHz (around 2000).

Then subsequent speed grades of FSBs and also those of the memories were chosen

as subsequent integral multiples of 133 MHz, such as

266 = 2 x 133

400 ~= 3 x 133

533 ~= 4 x 133

667 ~= 5 x 133

800 ~= 6 x 133

1067 ~= 7 x 133

1333 ~= 8 x 133

1600 ~= 9 x 133 etc.


2 2 2 2 speed grades 3

2.2.2.2 Speed grades (3)

Transfer rate(MT/s)

5000

DDR3

1600

DDR3

1333

2000

*

DDR2800

*

DDR2

667

1000

DDR2

533

*

DDR

400

*

DDR

333

*

500

DDR

266

*

*

SDRAM

133

*

200

SDRAM

100

~ 10*/10years

*

100

*

SDRAM

66

*

50

20

10

Year

96

97

98

99

2000

01

02

03

04

05

06

07

08

Rate of increasing the transfer rates in synchronous DRAMs

Figure 2.12: The evolution of peak transfer rates of parallel connected synchronous DRAMs

as manifested in Intel’s chipsets


2 2 2 2 speed grades 4

2.2.2.2 Speed grades (4)

Memory speed grades used in Intel’s multicore systems

Kind of attaching memory

(In Intel’s MC systems, typically)

Attaching memory

by parallel channels

Attaching memory

by serial channels

Using serial channels

with S/P converters

Memory is attached

to the MCH

Memory is attached

to the processor(s)

Using FB-DIMMs

Up to DDR2-667

Up to DDR3-1067

Up to DDR3-1600

Up to DDR2-667


2 2 2 4 dimm density 1

2.2.2.4 DIMM density (1)

Units 106

2000

4M

16M

64M

256M

1G

1500

Density: ~4×/4Y

256K

1M

64K

1000

500

16K

Year

1980

1985

1990

1995

2000

2005

2010

2015

2.2.2.4. DIMM density

a) Device density

Figure 2.13: Evolution of DRAM densities (Mbit) and no. of units shipped/year (Based on [23])


2 2 2 4 dimm density 2

2.2.2.4 DIMM density (2)

b) DIMM (module) density

Based on device densities of 1 to 4 8 Gb and with typical width of x4 to x16 (bits) DDR2 or

DDR3 modules provide typical densities of up to 8 or 16 GB.


2 2 2 5 use of ecc support 1

2.2.2.5Use of ECC support (1)

2.2.2.5 Use of ECC support

ECC basics

(as used in DIMMs)

Implemented as SEC-DED(Single Error Corretion Double Error Detection)

Single bit Error Correction

For D data bits P check-bits are added.

P

D

Figure: The code word

The minimum number of check-bits (P) for single bit error corection ?

Requirement:

2P ≥ the minimum number of states to be distinguished.


2 2 2 5 use of ecc support 2

2.2.2.5Use of ECC support (2)

The minimum number of states to be distinguished:

  • It is needed to specify the bit position of a possible single bit error in the code word

  • consisting of both data and check bits This requires D + P states

  • one additional state to specify the „no error” state.

the minimum number of states to be distinguished is: D + P + 1

Accordingly:

to implement single bit error correctionthe minimum number of check bits (P)

needs to satisfy the requirement:

2P ≥ D + P + 1


2 2 2 5 use of ecc support 3

2.2.2.5Use of ECC support (3)

Double bit error detection

an additional parity bit is needed to check for an additional error.

Then the minimum number of check-bits (CB) needed for SEC-DED is:

P = CB - 1

CB = P + 1

since

2P ≥ D + P + 1

2CB-1 ≥ D + CB -1 + 1

2CB-1 ≥ D + CB

Table 2.5: The number of check-bits (CB) needed for D data bits


Dezs sima 20 1 2 december

2.2.2.5Use of ECC support (4)

Supported memory features of DT and DP/MP platforms

DT memories typically do not support ECC or registered (buffered) DIMMs,

Servers make typically use ofregistered DIMMs with ECC protection.


Dezs sima 20 1 2 december

2.2.2.5Use of ECC support (5)

ECC

Register

Register

PLL

Typical implementation of ECC protected registered DIMMs(used typically in servers)

Main components

  • Two register chips, for buffering the address- and command lines

  • A PLL (Phase Locked Loop) unit for deskewing clock distribution.

Figure 2.14:Typical layout of a registered memory module with ECC [14]


2 2 2 6 use of registering 1

2.2.2.6Use of registering (1)

2.2.2.6 Use of registering

Problems arising while implementing higher memory capacities

Higher memory capacities need more modules

Higher loading the lines

Signal integrity problems

Buffering address and command lines,

Phase locked clocking of the modules


2 2 2 6 use of registering 2

2.2.2.6Use of registering (2)

Registering

Principle

Buffering address and control lines

  • to reduce signal loading in a memory channel

  • in order to increase the number of supported DIMM slots (max. mem. capacity),

  • needed first of all in servers,


2 2 2 6 use of registering 3

2.2.2.6Use of registering (3)

S

D

R

A

M

S

D

R

A

M

S

D

R

A

M

S

D

R

A

M

S

D

R

A

M

S

D

R

A

M

S

D

R

A

M

S

D

R

A

M

S

D

R

A

M

Data From / To Motherboard

PI6CV857PLL

PI74SSTV168

57 Register

PI74SSTV168

57 Register

Input ClockforMotherboard

Address ControlfromMotherboard

Address/ControlformMotherboard

Example: Block diagram of a registered DDR DIMM

Figure 2.17: Example. Block diagram of a registered DDR DIMM [16]


2 2 2 6 use of registering 4

2.2.2.6Use of registering (4)

Implementation of registering

By means of a register chip that buffers address and control lines

R

E

G

I

S

T

E

R

REGE: Register enable signal

Figure 2.15: Registered signals in case of an SDRAM memory module [15]

Note: Data (DQ) and data strobe (DQS) signals are not registered

as only address an control signals are common for all memory chips.


2 2 2 6 use of registering 5

2.2.2.6Use of registering (5)

Number of register chips required

  • Synchronous memory modules (SDRAM to DDR3 DIMMs) have about 20 – 30

  • address and control lines,

  • Register chips buffer usually 14 lines,

Typically, two register chips are needed per memory module [16].


2 2 2 6 use of registering 6

2.2.2.6Use of registering (6)

ECC

Register

Register

PLL

Typical layout of registered DIMMs

  • Two register chips, for buffering the address- and command lines

  • A PLL (Phase locked loop) unit for deskewing clock distribution.

Figure 2.16:Typical layout of a registered memory module with ECC [14]


2 2 2 6 use of registering 7

2.2.2.6Use of registering (7)

S

D

R

A

M

S

D

R

A

M

S

D

R

A

M

S

D

R

A

M

S

D

R

A

M

S

D

R

A

M

S

D

R

A

M

S

D

R

A

M

S

D

R

A

M

Data From / To Motherboard

PI6CV857PLL

PI74SSTV168

57 Register

PI74SSTV168

57 Register

Input ClockforMotherboard

Address ControlfromMotherboard

Address/ControlformMotherboard

Example: Block diagram of a registered DDR DIMM

Figure 2.17: Example. Block diagram of a registered DDR DIMM [16]


2 2 2 6 use of registering 8

2.2.2.6Use of registering (8)

ECC

Registered DIMM module with ECC

Figure 2.18:Registered DIMM module with ECC [14]


2 2 2 6 use of registering 9

2.2.2.6Use of registering (9)

Typical use of unregistered DIMMs (UDIMMs)

in desktops/laptops (Memory capacities: up to a few GB)

Typical use of registered DIMM (RDIMM)

in servers (Memory capacities: a few tens of GB to a few hundreds of GB)


Dezs sima 20 1 2 december

2.3. Buses interconnecting platform components


2 3 buses interconnecting platform components 1

2.3 Buses interconnecting platform components (1)

2.3 Buses interconnecting platform components

Use of buses in Intel’s DT/DP and MP platforms

Buses interconnecting

processors

(In NUMA topologies)

Buses interconnecting

processors to chipsets

Buses interconnecting

MCHs to ICHs

(In 2-part chipsets)

Xeon 6500

(Nehalem-EX)

(Becton)

Xeon E7-2800

(Westmere-EX)

or

SMB

SMB

SMB

SMB

Nehalem-EX (8C) Westmere-EX (10C)

Nehalem-EX (8C) Westmere-EX (10C)

QPI

SMB

SMB

SMB

SMB

QPI

QPI

SMI links

SMI links

DDR3-1067

DDR3-1067

7500 IOH

ME

SMI: Serial link between the processor

and the SMB

SMB: Scalable Memory Buffer with

Parallel/serial conversion

ESI

ICH10

Nehalem-EX aimed Boxboro-EX scalable DP server platform (for up to 10 cores)

Remark

Buses connecting the memory subsystem with the main body of the platforms are memory specific

interfaces and will be discussed in Section 4.


2 3 buses interconnecting platform components 2

2.3 Buses interconnecting platform components (2)

Implementation of buses used in Intel’s DT/DP and MP platforms

Parallel/serial bus

Parallel bus

Serial bus

(Point-to-point interconnection)

4-bit wide

(4 PCIe lanes)

64-bit wide

8-bit wide

16-bit wide

Used to interconnect

MCHs to ICHs

in previous platforms

Used to interconnect

processors to chipsets

or MCHs to ICHs

Used to interconnect

processors to processors

and processors to chipsets

Used to interconnect

processors to chipsets

in previous platforms

FSB

(Front Side Bus)

HI1.5

QPI

(Quick Path Interconnect)

QPI1.1

(Quick Path Interconnect v.1.1)

DMI

(Direct Media Interface)

ESI

(Enterprise System Interface)

DMI2

(Direct Media Interface 2.G.)


2 3 buses interconnecting platform components 3

2.3 Buses interconnecting platform components (3)

Buses used in Intel’s DT/DP/MP platforms

Buses interconnecting

processors

(In NUMA topologies)

Buses interconnecting

processors to chipsets

Buses interconnecting

MCHs to ICHs

(In 2-parts chipsets)

FSB (64-bit: 1993)

HI 1.5 (1999)

  • 64-bit wide

  • ~150 lines

  • 3.2-12.8 GB/s total

  • in both directions

  • 8-bit wide

  • 16 lines

  • 266 MB/stotal

  • in both directions

Parallel bus

Low-cost

systems

Parallel/serial bus

High-performance

systems

QPI (2008)

DMI/ESI (2008)2

DMI/ESI (20041)

QPI (2008)

  • 20 lanes

  • 84 lines

  • 9.6/11.72/12.8 GB/s

  • in each direction

  • 4 PCIe lanes

  • 18 lines

  • 1 GB/s/direction

  • 20 lanes

  • 84 lines

  • 9.6/11.72/12.8 GB/s

  • in each direction

  • 4 PCIe lanes

  • 18 lines

  • 1 GB/s/direction

Serial bus

QPI1.1 (2012?)

DMI2 (2011)

DMI2 (2011)

  • 4 PCIe lanes

  • 18 lines

  • 2 GB/s/direction

  • 4 PCIe lanes

  • 18 lines

  • 2 GB/s/direction

Specification na.


2 3 buses interconnecting platform components 4

2.3 Buses interconnecting platform components (4)

Remarks

1 DMI: Introduced as an interface between the MCH and the ICH first along with the ICH6,

supporting Pentium 4 Prescott processors, in 2004.

2 DMI: Introduced as an interface between the processors and the chipset first between

Nehalem-EP and the 34xxPCH, in 2008,

after the memory controllers were placed to the processor die.


2 3 buses interconnecting platform components 5

2.3 Buses interconnecting platform components (5)

S+

VCM

VREF

S-

t

t

t

Signaling used in buses

Signals

Voltage referenced

Differential

Single ended

Typ.voltage

swings

3.3-5 V

200-300 mV

600-800 mV

TTL (5 V)

FPM/EDO

LVDS

PCIe

QPI, DMI, ESI

FB-DIMMs

SSTL

SSTL2 (DDR)

SSTL1.8 (DDR2)

SSTL1.5 (DDR3)

RSL (RDRAM)

FSB

Signaling

system used

LVTTL (3.3 V)

FPM/EDO

SDRAM

HI1.5

DRSL

XDR (data)

Smaller voltage swings

LVDS: Low Voltage Differential Signaling LVTTL: Low Voltage TTL

(D)RSL: (Differential) Rambus Signaling Level SSTL: Stub Series Terminated Logic VCM: Common Mode Voltage VREF: Reference Voltage

Figure 2.4: Signal types used in MMs for control, address and data signals


2 3 buses interconnecting platform components 6

2.3 Buses interconnecting platform components (6)

Main features of parallel buses used in Intel’s MC platforms

FSB/HI 1.5: Bus type interconnects


2 3 buses interconnecting platform components 7

2.3 Buses interconnecting platform components (7)

Main features of serial buses used in Intel’s MC platforms

DMI/QPI: Point-to-point interconnection


2 3 buses interconnecting platform components 8

2.3 Buses interconnecting platform components (8)

Comparing main features of Intel’s FSB and QPI [9]

GTL+: A kind of voltage refenced signaling


2 3 buses interconnecting platform components 9

2.3 Buses interconnecting platform components (9)

Principle of LVDS signal transmission used in serial buses

Figure 2.5: LVDS Single Link Interface Circuit [10]


2 3 buses interconnecting platform components 10

2.3 Buses interconnecting platform components (10)

PCIe package format (data frames)

PCI Express Data Frame [10]

The related fields are:


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2.3 Buses interconnecting platform components (11)

TX Unidirectional link

RX Unidirectional link

16 data

2 protocol

2 CRC

Principle of the QuickPath Interconnect bus (QPI bus)

Figure 2.6: Signals of the QuickPath Interconnect bus (QPI-bus) [11]


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5. References


5 references 1

5. References (1)

[1]: Wikipedia: Centrino, http://en.wikipedia.org/wiki/Centrino

[2]: Industry Uniting Around Intel Server Architecture; Platform Initiatives Complement Strong

Intel IA-32 and IA-64 Targeted Processor Roadmap for 1999, Business Wire,

Febr. 24 1999, http://www.thefreelibrary.com/Industry+Uniting+Around+Intel+Server

+Architecture%3B+Platform...-a053949226

[3]: Intel Core 2 Duo Processor, http://www.intel.com/pressroom/kits/core2duo/

[4]: Keutzer K., Malik S., Newton R., Rabaey J., Sangiovanni-Vincentelli A., System Level Design:

Orthogonalization of Concerns and Platform-Based Design, IEEE Transactions on

Computer-Aided Design of Circuits and Systems, Vol. 19, No. 12, Dec. 2000, pp. 1-29.

[5]: Krazit T., Intel Sheds Light on 2005 Desktop Strategy, IDG News Service, Dec. 07 2004,

http://pcworld.about.net/news/Dec072004id118866.htm

[6]: Perich D., Intel Volume platforms Technology Leadership, Presentation at HP World 2004,

http://98.190.245.141:8080/Proceed/HPW04CD/papers/4194.pdf

[7] Powerful New Intel Server Platforms Feature Array Of Enterprise-Class Innovations. Intel’s

Press release, Aug. 2, 2004 ,

http://www.intel.com/pressroom/archive/releases/2004/20040802comp.htm

[8]: Smith S., Multi-Core Briefing, IDF Spring 2005, San Francisco, Press presentation,

March 12005, http://www.silentpcreview.com/article224-page2

[9]: An Introduction to the Intel QuickPath Interconnect, Jan. 2009, http://www.intel.com/

content/dam/doc/white-paper/quick-path-interconnect-introduction-paper.pdf

[10]: Davis L. PCI Express Bus,

http://www.interfacebus.com/PCI-Express-Bus-PCIe-Description.html


5 references 2

5. References (2)

[11]: Ng P. K., “High End Desktop Platform Design Overview for the Next GenerationIntel

Microarchitecture (Nehalem) Processor,” IDF Taipei, TDPS001, 2008,

http://intel.wingateweb.com/taiwan08/published/sessions/TDPS001/FA08%20IDF-

Taipei_TDPS001_100.pdf

[12]: Computing DRAM, Samsung.com, http://www.samsung.com/global/business/semiconductor

/products/dram/Products_ComputingDRAM.html

[13]: Samsung’s Green DDR3 – Solution 3, 20nm class 1.35V, Sept. 2011,

http://www.samsung.com/global/business/semiconductor/Greenmemory/Downloads/

Documents/downloads/green_ddr3_2011.pdf

[14]: DDR SDRAM Registered DIMM Design Specification, JEDEC Standard No. 21-C, Page

4.20.4-1, Jan. 2002, http://www.jedec.org

[15]: Datasheet, http://download.micron.com/pdf/datasheets/modules/sdram/

SD9C16_32x72.pdf

[16]: Solanki V., „Design Guide Lines for Registered DDR DIMM Module,” Application Note AN37,

Pericom, Nov. 2001, http://www.pericom.com/pdf/applications/AN037.pdf

[17]: Fisher S., “Technical Overview of the 45 nm Next Generation Intel Core Microarchitecture

(Penryn),” IDF 2007, ITPS001, http://isdlibrary.intel-dispatch.com/isd/89/45nm.pdf

[18]: Razin A., Core, Nehalem, Gesher. Intel: New Architecture Every Two Years,

Xbit Laboratories, 04/28/2006,

http://www.xbitlabs.com/news/cpu/display/20060428162855.html

[19]: Haas, J. & Vogt P., Fully buffered DIMM Technology Moves Enterprise Platforms to the

Next Level,” Technology Intel Magazine, March 2005, pp. 1-7


5 references 3

5. References (3)

[20]: „Introducing FB-DIMM Memory: Birth of Serial RAM?,” PCStats, Dec. 23, 2005,

http://www.pcstats.com/articleview.cfm?articleid=1812&page=1

[21]: McTague M. & David H., „ Fully Buffered DIMM (FB-DIMM) Design Considerations,”

Febr. 18, 2004, Intel Developer Forum, http://www.idt.com/content/OSA-S009.pdf

[22]: Ganesh B., Jaleel A., Wang D., Jacob B., Fully-Buffered DIMM Memory Architectures:

Understanding Mechanisms, Overheads and Scaling, 2007,

[23]: DRAM Pricing – A White Paper, Tachyon Semiconductors,

http://www.tachyonsemi.com/about/papers/DRAM%Pricing.pdf


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