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FX to FX2: A Comparison. Agenda. Block diagram Evolution Hardware Firmware Wrap-up. EZ-USB FX Block Diagram. FX. High Performance Micro Using Standard Tools. Uses Low-Cost Crystal. Up to 48 MBytes/s Burst Rates. 12 MHz XTAL. Memory Expansion or Data Buffer Ports. EZ-USB. FX.
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Agenda • Block diagram • Evolution • Hardware • Firmware • Wrap-up
EZ-USB FX Block Diagram FX High Performance Micro Using Standard Tools Uses Low-Cost Crystal Up to 48 MBytes/s Burst Rates 12 MHz XTAL Memory Expansion or Data BufferPorts EZ-USB FX 8051 Core 24/48 MHz, 4 clocks/cycle Address (16) X4 PLL Data(8) Abundant I/O Including 2 UARTS DMA Engine I/O Ports (40) General Programmable I/F to any ASIC/DSP or bus standards such as ATAPI, EPP, etc. Address (16) / Data Bus (8) USB 1.1 XCVR D+ GPIF 4 KB / 8KB RAM D- CY Smart USB Engine Four 64 bytes FIFO 8/16 bits 2 KB FIFO Master or Slave Operation I2C Compatible 1K Double-Buffer Isochronous Support Peripheral I/O Flexibility "Soft Configuration” Easy Firmware Changes Enhanced USB Core Simplifies 8051 Code
EZ-USB FX2Block Diagram FX2 High Performance Micro Using standard tools with low power options Uses Low-Cost Crystal Peripheral I/O Flexibility 24 MHz XTAL EZ-USB FX2 I2C - Compatible Master Memory Expansion or Data Buffer Ports /0.5 /1.0 /2.0 X20 PLL 8051 Core 12/24/48 MHz 4 clocks/cycle Address (16) Vcc Data (8) 1.5k Abundant I/O Including 2 UARTS connect Address (16) / Data Bus (8) for full Additional I/Os (24) speed USB 2.0 XCVR ADDR (9) D+ GPIF 8.5kB RAM General Programmable Interface to any ASIC/DSP or bus standards such as ATAPI, EPP, etc. RDY (6) D- CY Smart USB Engine CTL (6) 4kB 8/16 FIFO FIFO and Endpoint Memory (Master or Slave Operation) Enhanced USB Core Simplifies 8051 Code "Soft Configuration” Easy Firmware Changes
Microprocessor control EZ-USB FX RAM/FIFO access Endpoint Interface Outside USB DMA FIFOS FIFO World (24 kilobits) (2 kilobits) (b) USB 1.1 Full Speed Microprocessor EZ-USB FX2 RAM/FIFO access Endpoint Outside USB FIFOS World (36 kilobits) (c) USB 2.0--no time wasted transferring data between FIFOS EZ-USB FX2Architectural Evolution Endpoint Outside EZ-USB USB Microprocessor FIFOS World (a) USB 1.1 Full Speed
FX to FX2Hardware - General • Not pin compatible • Internal resistor for DISCON pin • Programmable WAKEUP with multiple sources • Firmware SUSPEND • Finally 115k and 230k baud internally with dedicated pins
FX to FX2Hardware - Slave FIFOs • Dedicated PKTEND pin • More flags with more programmable flexibility • Two address pins to select 1 of 4 FIFOs • Same flexible programmable polarity for control pins
FX to FX2Hardware - GPIF • GPIF sampling or sync clock either 30 or 48 MHz • More address lines (9 vs. 6) • GPIF signals are not muxed with GPIO signals
FX vs. FX2Hardware - I/F Clocking • CLKOUT either 12, 24, or 48 MHz • IFCLK can either be an input or an output
FX vs. FX2Hardware - DK • CPLD instead of 22V10 • Same BRKPT LED plus four additional LED’s • Switch selectable EEPROM size
FX to FX2Firmware - USB • Endpoint size and buffering is programmable • Auto In/Out to take 8051 out of data path • No separate ISO buffers • Can turn off SOF generation • Better setup data pointer • No more busy bits • From 16 endpoints to 7
FX vs. FX2Firmware - Slave FIFOs • FIFOs individually selectable 8/16 wide • FIFO empty + 1 and full -1 flags • FIFO status registers in SFR space
FX vs. FX2Firmware - GPIF • New GPIF long transfer mode • Can now check all flags in decision point • GPIF trigger now in SFR space
FX to FX2Firmware - 8051 • Full 8k of internal memory for code & xdata • More registers in SFR space • I/O ports in SFR space only • 8051 clock rate either 12, 24, or 48 MHz • No more DMA • Two autopointers
