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NCTU, CS VLSI Information Processing Research Lab. Low-Cost Graphics Processor. 研究生 :. 指導教授 : 范倫達 博士. The Proposed Folded Type DFT/IDFT Architecture. ABSTRACT Introduction NEW Recursive DFT/IDFT architecture

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Low-Cost Graphics Processor

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Low cost graphics processor

NCTU, CS VLSI Information Processing Research Lab

Low-Cost Graphics Processor

研究生:

指導教授: 范倫達 博士

The Proposed Folded Type DFT/IDFT Architecture

  • ABSTRACT

    Introduction

  • NEW Recursive DFT/IDFT architecture

    • Low computation cycle

      • 1/2: Chebyshev polynomial

      • 2/N: Folded architecture

    • High speed

      • Register-splitting and computation-sharing scheme

        New Recursive Formula For DFT/IDFT

        Challenges: High-Performance and Area-Aware VLSI

In this work,

  • Data Buffer

    • 64 16-bit word length complex data storage

  • Control Unit

    • Clock Gated Control

    • Sequence Controller

    • Parameter Controller

  • 32 PEs32 PEs

    • Pre-processing for Sk and rk

    • TWO PEs for DST and DCT

  • Proposed two design

    • Core Type: N2/2

    • Folded Architecture: N

  • Regularity construct by the N/2 PEs in parallel

  • No intermediate register bank needed

  • Further reduce the computation cycle to N

    N = (N2/2) / (N/2)

  • Processor latency: 64 clock

    (Computation cycles)

  • Critical Path: Tm+2Ta

,where

  • Simulation and Implementation Results

    • Lower round of error due to the fewest computation cycle

    • AWGN Channel

  • 212/106-point recursive DFT/IDFT Design

    • For DTMF Detector System

The Proposed Recursive DFT formula:

Comparisons Results

The Proposed Recursive IDFT formula:

  • Conclusion

  • A new recursive DFT/IDFT architecture based on the hybrid of Input strength reduction, Chebyshev polynomial and register-splitting schemes is proposed.

  • The proposed VLSI algorithms lead to the fewest computation cycle and higher speed than others.

  • The proposed core type and folding type recursive architecture with regular organization is certainly amenable to VLSI implementation.

References

[1]M. D. Felder, J. C. Mason, and B. L. Evans, “Efficient dual-tone multifrequency detection using the nonuniform discrete Fourier transform,”IEEE Signal Processing Lett., vol. 5, pp. 160-163, Jul. 1998.

[2]G. Goertzel, “An algorithm for the evaluation of finite trigonometric series,” American Math. Monthly, vol. 65, pp. 34-35, Jan. 1958.

[3]V. V. Cizek, “Recursive calculation of Fourier transform of discrete signal,” IEEE Int. Conf. Acoustics, Speech, and Signal Processing, May 1982, pp. 28-31.

[4]L. D. Van and C. C. Yang, "High-speed area-efficient recursive DFT/IDFT architectures," in Proc. IEEE Int. Symp. Circuits Syst., May 2004, vol. 3, pp. 357-360, Vancuover, Canada.

[5]H. V. Sorensen, D. L. Jones, M. T. Heideman, C S. Burrus, “Real-valued fast Fourier transform algorithms,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 35, pp. 849-863, June 1987.

[6]C. H. Chen, B. D. Liu, J. F. Yang, and J. L. Wang, “Efficient Recursive Structures for forward and inverse discrete cosine transform,” IEEE Trans. Signal Processing, vol. 52, pp. 2665-2669, Sep. 2004.

The Proposed Core-Type DFT Architecture

The Proposed Core-Type IDFT Architecture

Achieve

Cost

&

Speed


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