Design of a Radiation-Tolerant Low-Power Transceiver

1. MAPLD 2001 Design of a Radiation-Tolerant Low-Power Transceiver D. Weigand, M. Harlacher ITT Industries Advanced Engineering & Sciences Reston, VA 11 September 2001

2. Acknowledgements • NASA Earth Science Technology Office (ESTO) • Adesh Singhal (Glenn Research Center) • Bob Bauer (Glenn Research Center) • Steve Smith • Mike Pasciuto • NASA Goddard Space Flight Center (GSFC) • Dave Zillig • Roger Flaherty • ITT Industries Advanced Engineering & Sciences • Dr. Richard Orr • Dr. Ted Benjamin • Scott Casteel

3. Outline Background The Low Power Transceiver (LPT) The Radiation-Tolerant LPT (rLPT) The rLPT DSP Module Design Approach The Future Summary

4. Background • NASA’s Office of Earth Sciences (OES) Vision—the Sensorweb • Multiple, small, less-expensive spacecraft • Network of space instruments • Provides multiple vantage points (e.g., LEO, MEO, GEO) • Achieves reliability through redundancy • Vision requires small, highly integrated, reprogrammable, multi-purpose communications and navigation spacecraft payloads for a variety of orbits

5. Introduction to the Low-Power Transceiver (LPT) • LPT is a collection of interchangeable PC/104 hardware modules that form a software programmable platform for communication and navigation functions • Simultaneously processes multiple RF bands in the TX or RX direction • Simultaneously processes multiple data channels within each RF band • Modular architecture allows flexibility of signal processing resources • Baseline configuration includes • 12 channel GPS receiver • 4 dedicated communications channels • Primary goals—low power consumption, small form factor, and reduced mass • Originally developed by NASA GSFC and ITT Industries, the LPT is evolving to meet the needs of numerous terrestrial, airborne, and space based users and missions

6. LPT Development Overview • Evolution of the LPT program is producing “generations” of the hardware platform • Each new generation provides an improved platform on which increasingly sophisticated signal processing may be used to solve complex communications and/or navigation problems • Improvements in efficiency are obtained by reducing the size, weight and power of subsequent generations • Each new generation is an “enabler” for a new objective or operations requirement • 1st Generation • First to integrate the functions of communication and navigation • Enabled new operations concepts including space-based range safety • 2nd Generation • Expanded RF and data channel capacity enables sophisticated inter- and intra-formation communication and navigation concepts for formation flying • Incorporates advanced phased array beamforming, multi-user detection and a RAKE receiver • 3rd Generation • Enables migration to fault-tolerant hardware and software as required by long-term space applications • Significantly improves RF and data channel density and flexibility

7. RF Receive Card ~6 MHZ IF BW ~3 MHZ Low Pass BW A/D Down- converter (D/C) D/C Virtex-E FPGA (2000K Gates) Virtex-E FPGA (2000K Gates) TI DSP 2x100 MIPS S-band in IF A/D • Mux • Sequential High-Speed Transversal Filter • Dual Channel Spread-Spectrum Modulator • Potential for P/Y Code Correlator • Parallel Code & Frequency Acquisition Engine • Sequential Demodulator • Sequential Viterbi Decoder • FFT Processing • Metric Generation • Data Interface • Data Formatting • Configuration Control Data Out D/C D/C A/D L-band in IF A/D Freq. Synthesis Freq. Synthesis Data in S-band out PA Upconvert D/A RF Transmit Card Digital Card Weight: 2 kg; Power consumption (without PA): 5 watts; 1 watt PA: 5 watts DC Existing 2nd Generation LPT Architecture

8. Goal—maintain current LPT functional capabilities & reprogrammability in a radiation-tolerant design Approach—address radiation tolerance of each LPT module independently Key Technologies Areas Power supply (complete) Incorporate existing rad-hard components RF hardware Inherent immunity of many parts Digital hardware (most susceptible to radiation) FPGAs (primary focus of paper) DSPs (secondary focus of paper) A/D and D/A converters Memories Evolution to a Radiation-Tolerant LPT (rLPT)

9. rLPT DSP Module Design Approach • Goal—incorporate radiation-tolerance in next generation DSP module • Current (2nd Gen) LPT DSP Module Design • All signal processing in FPGAs and DSP • Functionality fully reconfigurable • Future (3rd Gen) rLPT DSP Module Design • Use radiation-hardened FPGAs to host LPT signal processing • Xilinx FPGA • Size and speed appropriate for LPT signal processing • Maintains reconfigurable functionality • Actel FPGA • Provides availability at power-on for control functions • Current DSP not available in radiation-tolerant version • Identify radiation-hardened DSP or • Move functions to radiation-hardened FPGAs

10. Radiation effects on Xilinx QPRO-plus FPGAs (Virtex-E) TID immune to >300 krads(Si) SEL immune to 120 MeV-cm2/mg Susceptible to SEUs (mitigation required) Xilinx FPGA Architecture CLBs, Block RAM, and I/O Blocks Programmable routing resources Flip-flops Configuration control logic Types of SEUs Configuration upsets User logic upsets Architectural upsets Also known as single event functional interrupts (SEFIs) Radiation Effects on Reconfigurable Xilinx FPGAs

11. Failure Modes and Effects Analysis

12. SEU Mitigation in Xilinx Virtex FPGAs • SEUs are mitigated with judicious combination of techniques • Partial reconfiguration (PRC) scrubbing • Triple-module redundancy (TMR) • Approach has been proven to correct all SEUs in Virtex FPGA • The only functional upsets are caused by SEFIs

13. Expected Virtex POR SEFI Rates for Typical Orbits

14. Use of LUT-RAM in TMR Design • Xilinx discourages using LUT-RAM in TMR design • PRC scrubbing overwrites dynamic LUT-RAM contents • LPT design uses LUT-RAM for design efficiency (e.g., shift registers) • Insufficient Block RAM resources to move all LUT-RAM memory to Block RAM • ITT Industries’ Approach • Position redundant LUT-RAMs in independent columns of configuration bitstream • Refresh redundant LUT-RAMs before any two LUT-RAMs are overwritten with PRC scrub

15. Radiation-Tolerant DSP Design • Second generation LPT uses 200 MIPS TI TMS320C5421 DSP • Currently hosts a significant portion of module’s signal processing • No radiation-tolerant version of this DSP available • Radiation-Tolerant DSP Solution • Move as many DSP functions to FPGA (e.g., FFT, tracking loops) • Implement soft processor core(s) in radiation-tolerant FPGA(s) • Soft Processor Implementation • Implement modest soft-processor core (e.g., 8051) in Actel FPGA • Controls all board configurations • Mentor Graphics Inventura Warp8051 uses 33% of RT54SX72S • Additional signal processing implemented in larger soft-processor core in Xilinx FPGA • TMR version of core is necessary • Processor necessary for signal processing beyond 2nd generation capability

16. The Future of LPT • Fourth Generation LPT—Miniature Transceiver (MinT) • Reduce volume from 100 cubic inches to 8 cubic inches • Expanded signal processing capabilities • Targeting reconfigurable space applications (e.g., nano-satellites) • Future developments rely upon continued advances in COTS component technology • Increase in device speed and density • Decrease in power consumption and device size • Improvement in radiation-performance

17. Summary • The radiation-tolerant LPT will meet the needs of current and future space applications • Use of radiation-tolerant COTS devices and application of fault-mitigation techniques results in reliable system with high capability • Continued advances in component technology will facilitate the development of systems that meet the growing requirements of spacecraft missions

18. References • Schoeberl, Mark, et al, “Earth Science Vision Initiative” NASA HQ Code Y and NASA GSFC, September 24, 1999. • E. Fuller, M. Caffrey, A. Salazar, C. Carmichael, J. Fabula, “Radiation Testing Update, SEU Mitigation, and Availability Analysis of the Virtex FPGA for Space Reconfigurable Computing,” MAPLD International Conference 2000, September 2000. • Carmichael, Carl, “Triple Module Redundancy Design Techniques for Virtex FPGAs”, Xilinx Application Note XAPP197, June 2001.