Reliability of Antifuse-Based field Programmable Gate Arrays for Military and Aerospace Applications
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Reliability of Antifuse-Based field Programmable Gate Arrays for Military and Aerospace Applications. John McCollum, Roy Lambertson, Jeewicka Ranweera, Jennifer Moriarta, Jih-Jong Wang, Frank Hawley, and Arun Kundu Actel Corporation.

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Reliability of Antifuse-Based field Programmable Gate Arrays for Military and Aerospace Applications

John McCollum, Roy Lambertson, Jeewicka Ranweera, Jennifer Moriarta, Jih-Jong Wang, Frank Hawley, and Arun Kundu

Actel Corporation

Figure1


Figure2


Manufacturer responsibility
Manufacturer Responsibility responsible for the content of an FPGA

  • Antifuses are an addition to the base CMOS process

  • Reliability of the ONO antifuse

  • There are two states that must be reliable

    • Open

    • Short

Figure3


N+ Polysilicon responsible for the content of an FPGA

Oxide

Nitride

Oxide

N+ Diffusion

ONO Antifuse

Figure4


ONO Antifuse Photomicrograph responsible for the content of an FPGA

Figure5


Figure responsible for the content of an FPGA6


Programmed State of ONO responsible for the content of an FPGA

Figure7


Note: No Switch off responsible for the content of an FPGA

Heating of Filament

Programmed at 5mA

Figure8


ONO Antifuse Switch off Test responsible for the content of an FPGA

Figure9



SEDR Curve

90A Thickness

Typical is 96A

Figure11


Figure12


Unprogrammed Antifuse Modules)

Via to Metal 4

Antifuse

Metal 3

Figure13


Life of the Universe Modules)

Data indicates that this line

actually turns up

Figure14


Programmed Antifuse Modules)

Figure15


Data showing that switch off the metal Antifuse Modules)

is over designed by at least a factor of 2

Figure16


SEDR of the Metal to Metal Antifuse Modules)

No failure

SXS shows one fail

at 2.85V

max spec is 2.75V

Figure17


  • Since BVG (Break Down Voltage) of ONO was lower than gate oxide no antifuses are connected to pins

  • ESD thus achieved Class 2 >2000 Volts

  • Actel however discovered PID (Process Induced Damage) in Fabs

  • Implanters and Plasma Etchers could produce 20 volts on the wafer and destroy the ONO

  • Actel worked with the Fabs and solved this problem

  • Additionally Actel voltage stresses each part at Wafer Sort and Final Test to eliminate all antifuse defects

Figure18


Nominal BVG oxide no antifuses are connected to pins

PID tale

Figure19


Figure20


Apparent turn up is due Failures

to less time to collect

long term data

Figure21


With ten years of production of Failures

Multi-Layer Aluminum the process

is very mature even though

it has been scaled

Early defects related to via failures

Figure22


Due to the high level of integration Failures

modern ICs are have progressed

dramatically

Note: no failures

Figure23


  • All tracks

  • All modules

  • All clocks

  • All programming circuits

  • All I/Os

  • All isolation transistors

  • The charge pump

  • All antifuses in the open state

  • All antifuses are stressed

  • A column of circuits is programmed (binning circuit) to verify programming

Figure24


Fault Coverage to unacceptable failure rates

Figure25


  • During programming a small fraction of antifuses will fail to program

  • Once the programmer passes a part it is guaranteed to be 100% functional

  • Tests are performed to verify the correct antifuse is programmed and is the correct impedance

  • Additional tests are done to verify that no other antifuse was erroneously programmed or any circuit damage was done

Figure26


  • CAE tools are reliable in translating RTL code to a logic design, but may pitfalls await the designer

  • Behavior level code would be less prone to bugs, but it will not be very efficient in silicon use or very fast - hence not much demand

  • Remember with FPGAs YOU are an IC designer

  • Following are few examples of pitfalls

Figure27


Without “Preserve” VHDL will delete this buffer design, but may pitfalls await the designer

Q

D

Q

D

>CLK

>CLK

High Skew Clock

A lot of emphasis needs to be placed of timing analysis!!

Figure28


Figure29


Figure30


Figure31


Figure32


Figure33


  • RTSXS have new features to make it power-up friendly while the charge pump is turning on

    • Outputs are tristated

    • Logic Modules are in standby

    • Outputs can be programmed to source or sink 50 a

    • Once Charge pump has reached operating voltage the modules are activated and the outputs become valid with no glitches

Figure34


  • Every FPGA manufacturer will tell their customers “use fully synchronous design”

  • Yet many designers don’t or manage to avoid fully synchronous design points at critical interfaces

  • The successful designer will learn his CAE tools and the target FPGA and follow good design practice

Figure35


User testing
User Testing fully synchronous design”

  • FLIP FLOPs can remember their last state up to 24 hours

  • Set flip flops to the opposite state of the desired power-up state for one hour before power-down followed by the power-up sequence

  • Power-on reset signals should not be applied until the power supplies have reached spec.

Figure36


Summary
Summary fully synchronous design”

  • Devices and CAE tools have improved tremendously in 30 years.

  • Very high levels of integration have made systems more reliable

  • ICs and CAE tools benefit from multiple users to scrub defects from the circuits

  • FPGAs have made the system designer an IC designer - ultimately the system reliability rests with him

Figure37


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