Hayet KEBBATI
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Data Flow Reduction and Signal Sparsification in MAPS. Hayet KEBBATI (GSI/IReS). Pixel Sensors applied to vertex detector. Hybrid Pixel Detectors. Fast readout and radiation hardness device , Sizeable pixel pitch due to readout circuitry surface, High material budget.

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Data Flow Reduction and Signal Sparsification in MAPS

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Data flow reduction and signal sparsification in maps

Hayet KEBBATI

Data Flow Reduction and Signal

Sparsification in MAPS

Hayet KEBBATI (GSI/IReS)


Data flow reduction and signal sparsification in maps

Hayet KEBBATI

Pixel Sensors applied to vertex detector

  • Hybrid Pixel Detectors

  • Fast readout and radiation hardness device,

  • Sizeable pixel pitch due to readout circuitry surface,

  • High material budget.

  • Charge Coupled Devices -CCD-

  • High density due to reduced pitch size,

  • Poor radiation hardnessand long readout time.

  • Monolitic Active Pixel Sensors -MAPS-

  • Benefits from constant decrease of technology size  higher pitch density,

  • Can be thinned down to the thickness wanted => less material budget compared to hybrid devices,

  • Fast readout and radiation tolerant compared to CCD,

  • But radiation hardness always far behind hybrid devices,

  • Cost-effective and easily available CMOS Process.


Data flow reduction and signal sparsification in maps

Hayet KEBBATI

CMOS Sensor -MAPS- : Data Flow Reduction

  • At the first Silicon tracking Station (5cm), particle densities have values up to 2 hits/mm².event,

  • Fast readout (100ns/event)  Huge data flow 1.6 Tera bits/sec (output size=1 bit),

  • Hit Extraction and data sparsification  Data flow of 8 Giga bits/sec

  • Implementation of on-chip processing forming a System on Chip

  • Parallel readout  40 transmission lines per reticle (20mmx20mm), Freq=200 MHz (output size=1 bits)

System on a Chip (SoC)

Sensor

Signal

Processing Part

Interface Part (ADC)

Analog part

Digital Part


Data flow reduction and signal sparsification in maps

Hayet KEBBATI

Smart Detector Reticle

Matrix of Pixel

Band Height of sensitive part

B1

Sensitive part

ADC

Control ELN

Sparcification

Control and processing part

Band Height of non-sensitive part

Memori-sation

B2

  • Control and address Electronics

  • Fast signal processing and data sparsification  Signal digitalisation

  • Storage threshold values needed during data sparsification

  • Surface ratio (B2/B1) must be as small as possible


Data flow reduction and signal sparsification in maps

Hayet KEBBATI

vdd

sample

read

Vout

Vx

VA

Cclamp

Cac

clamp

gnd

Vclamp

Csample

SF

SF

2 diodes’s Self reverse bias charge sensitive element

gnd

gnd

Charge Sensitive Element :

CDS with clamping capacitor architecture

  • nwell/p-epi diode biased by a bias forward diode to convert particle charge to voltage,

  • Noise sources : shot noise, FPN, flicker noise and thermal => CDS technique

  • On pixel CDS and amplification => good signal to noise ratio and Treadout=100ns.


Data flow reduction and signal sparsification in maps

Hayet KEBBATI

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 Clusters

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Signal Sparsification Method

seed_thre=7 mv

cluster_thre=20 mv

Hit2

3 Steps : 1) Scanning clusters of 3x3 pixels

2) Compare pixels and clusters with seed threshold and cluster threshold value

3) Extract valid clusters


Data flow reduction and signal sparsification in maps

Hayet KEBBATI

Data Flow with On-chip Processing

Rocc is the hit occupancy rate = number of hits / total number of pixels

Wadr is the binary length of the address of the pixel position

Wpix is the binary length of the signal corresponding to the pixel voltage


Data flow reduction and signal sparsification in maps

Hayet KEBBATI

Sub-bloc Detector Structure

1000 columns

(20 mm)

Pitch = 20 µm

100 rows

Sensitive part

(2 mm)

1000 3bits ADC

Seed pixel and cluster Comparisons

Control and processing part

Cluster Extraction

Threshold values Memorisation

  • Pixel Readout time = 100ns => Readout time = 10 µs

    => occupancy rate up to 8% at station 1 closest to the beam

  • Column parallel readout,

  • Digitalization of the output data of each column (3 bits ADC).


Data flow reduction and signal sparsification in maps

Hayet KEBBATI

10 MHz

ADC

ADC

ADC

ADC

ADC

ADC

ADC

ADC

ADC

ADC

ADC

ADC

ADC

ADC

ADC

ADC

128

128

8

50 MHz

128

128

OR Gates

Tree

OR Gates

Tree

FSM

FSM

FIFO

FIFO

+

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counter

200 MHz

Data Sparsification Implementation results (0.35 µm)

  • Surface = 20mm2

  • Processing surface to sensitive surface ratio=1/2


Data flow reduction and signal sparsification in maps

Hayet KEBBATI

data

adr

write

adr

bit line

bit line

write

pre

read

gnd

data

valid data

read

SDRAM Memory Strucure

DRAM cell

row decoder

row decoder

row decoder

row decoder

column decoder

3 T DRAM 3.5 x 5.5 m = 2.5 x 3.92

column mux, write buffers, sense amplifiers,

  • Read Cycle

  • Write Cycle


Data flow reduction and signal sparsification in maps

Hayet KEBBATI

SDRAM Implementation Results

  • Memory of 512x26 bits in 0.25µm technology

  • Regular layout with silicon surface saving

  • Test data maintain time in DRAM cells

  • Test of circuit behavior under radiation : number and type of errors  detection and correction bits

Surface : 320µmx930µm

Access delay : 2.5 ns

Power dissipation: 7 mW


Data flow reduction and signal sparsification in maps

Hayet KEBBATI

Summary

  • Real-time data processing

    • Readout time = 10µs => hit occupancy rate up to 8% in worst case

    • Processing surface to sensitive surface ratio = ½

    • To improve the ratio :

      • Increase the pitch  hit occupancy rate rise

      • Parallel readout by 2 rows High power dissipation

Options to reduce hit occupancy:

  • Optimize STS geometry to avoid hot spots

    ? Use hybrid pixels in the hottest area

  • SDRAM design in 0.25 µm technology

    • Surface = 320µmx930µm

    • Access time = 2.5 ns


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