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Trigger Validation Board PVSS panels tutorial PowerPoint PPT Presentation


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Trigger Validation Board PVSS panels tutorial. TVB components. 2 FPGA controls : FPGA HCAL hadron trigger FPGA EPPI electron , photon , pi0 , Global PI0 Delay chips to be set for each FPGA Look up tables for each FPGA (LUT) Optical mezzanine Temperature.

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Trigger Validation Board PVSS panels tutorial

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Trigger validation board pvss panels tutorial

Trigger Validation Board

PVSS panels tutorial


Tvb components

TVB components

  • 2 FPGA controls :

    • FPGA HCAL hadron trigger

    • FPGA EPPI electron , photon , pi0 , Global PI0

  • Delay chips to be set for each FPGA

  • Look up tables for each FPGA (LUT)

  • Optical mezzanine

  • Temperature


Fpga hcal elements to be set

FPGA HCAL elements to be set

  • FPGA HCAL:

    • Ensure the HCAL+ECAL sum of corresponding pads

      • Card configuration : Which inputs are filled

      • Choice of signal front ( rising-falling)

      • Choice of the delay pipe line for trigger : setting of delay for each entry ( HCAL and ECAL)

      • PSSPD entries not used ( masked)

      • The phase adjustement to ensure full data transmission

  • Elements are set by default through recipees


Fpga eppi elements to be set

FPGA EPPI elements to be set

  • FPGA EPPI:

    • Select the highest electron, photon, pi0, global pi0 for each validation board candidate according to the PS/SPD pattern and ECAL energy. Parameters to be set :

      • Card configuration : Which inputs are filled

      • Choice of signal front ( rising-falling)

      • Choice of the delay pipe line for trigger : setting of delay for each entry ( PSSPD & ECAL)

      • The phase adjustement to ensure full data transmission

  • Elements are set by default through recipees


The road to the tvb panel

The road to the TVB panel

Main project CA1-EC1…:

2TVB /crate

TVB number : (crate-(8(c-side), 15(A-side) )*2 + ( o(left) +1(right))


Piquet materials

Piquet materials

- A panel summarize the setting and check their status in respect to the recipee : piquet summary

  • 2 panels allow to have more details on FPGA and are used for recipee update when channels masking is required

  • HCAL FPGA

  • EPPI FPGA


Piquet summary 0

Piquet summary (0)

  • Info générales

Summary of settings and

Status of front and delays

Comparison to recipee

Click to update the summary


Piquet summary general info 1

Piquet Summary : general info (1)

General info on crate naming & location

Recipee info

When clicking a window of all files used in recipee appears

TVB FPGA version of firmware

To be check after TVB change


Piquet summary comparison to recipee 2

Piquet Summary : Comparison to recipee(2)

Check FPGA when red

Settings are not the one

expected in recipee

Right part give more info:

Comparison to the

Recipee front settings

Comparison to the recipee

Delay setting.

Also the FPGA HCAL (EPPI) panel can be consulted


Piquet summary comparison to recipee 3

Piquet Summary: Comparison to recipee (3)

Check the optical link

configuration .

More info in GOL panel.

Red if not the recipee

Configuration; reconfigure

If persist check with L0 piquet

Card & mezzanine temperature

More information on temprature

Panel .

This information may not be reliable

Check delay chip set FPGA phase if red. Reconfigure .

If the error persist go to expert.

More info on delay chip page

In case of laser fault ( from the mezzanine) , check with

L0 if data affected.


Hcal pga panel

HCAL PGA panel

Give the information on the delay used channel per channel

compare to recipee Green if ok

BXid offset & idle are part of the recipee and checked in the summary panel


Trigger validation board pvss panels tutorial

FPGA informations panel:

Mezzanine status panel

All links should be green

12


Trigger validation board pvss panels tutorial

Temperature panels:

1. under the mezzanine

2. between FPGA

A temperature of -0.5 means that all bits are on . Reading error of the temperature. To be fixed be expert .

13


Delay chip page info

Delay chip page ( info )

Get the current delay setting

Values expected by recipee

Possibility of forcing delay chip reset


Trigger validation board pvss panels tutorial

Expert panel

GOL mezzanine panels:

1. EPPI

2. HCAL

Allow to change control on

Optical links

15


Trigger validation board pvss panels tutorial

Delay chip and LUT panel:

Read and change delay settings

Value in use

Reset delay chip

Read from file

Save new settings

Reload the LUT

manually

16


Trigger validation board pvss panels tutorial

FPGA informations panel:

Mezzanine status panel

All links should be green


Trigger validation board pvss panels tutorial

Triple Voting panels:

1. EPPI

2. HCAL

Allow to read if

Among the 3 register one

Has changed

To be efficient

The read command

Should be performed


Trigger validation board pvss panels tutorial

Recipes panel:

By default the files are the one loaded for the configuration

Will change the recipe

For the cards

Will redo the whole

Recipe (10min)


A tvb does not want to configure

A TVB does not want to configure

  • Go to the Summary panel . Identify the faulty part

  • Call expert

    A TVB configure but L0 is complaining

    Check no faulty part in the summary channel

    If some call the expert.


Trigger is too high or 0

Trigger is too high or 0

  • Check the Summary page

    • If faulty , reconfigure the whole crate

    • Trigger too high ask L0 the link with high rate

    • Identify the High or faulty link ‘ Electron ,photon .. Or HCAL using the Summary page and L0 info

    • Check the GOL status

    • Report to L0 & expert

  • The trigger is high coming from a faulty input to TVB)

    • Mask the fault input

    • Save the configuration ( next slide)

    • Next time the recipee will use this new configuration


Mask an input channel to the tvb

Mask an input channel to the TVB

  • HCALFPGA panel

  • EPPIFPGA

1. Get all

2. Mask the channel

3. Apply register

4.Update the recipee

The next time the recipee is called the change will still be there


Missing source complain from trigger people

Missing source complain from trigger people

  • Check Summary page

  • Check GOL status on HCAL or EPPI

  • Inspect the HCAL or EPPI FPGA settings /recipee (done automatically )

  • Verify the input is not masked


  • Login