Oscillator & Timing. 4K Program Memory. 128 bytes RAM. 2x16 bit Timers. INTERNAL DATA BUS. 80C51 CPU. 64K byte Expansion Control. Programmable I/O (32 Pins). Serial I/O. 5 x Interrupts. Architecture of the 8051.
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I/O (32 Pins)
5 x InterruptsArchitecture of the 8051
Oscillator circuit times the CPU: Typical 12 MHz. Note that one machine cycle is 6 states, which are 12 clocks.
CPU: Has instruction decoder, ALU, PC and Boolean Processor, Instruction register and interrupt SFRs Interrupt Priority Register (IPR) and Interrupt Enable Register (IEC).
4K PROM: Expandable to 64K using DPTR/PC + MOVX instruction.
128 byte Scratchpad + 128 Addressable bits in the LSByte of SFRs. SFRs include registers A, B, PSW, SP, DPH/DPL
2x16 bit timers: These are controlled with SFRs TMOD and TCON. There is also an interrupt vector for each timer overflow.
Expansioncontrol is capable of supporting 64Kbyte of external ROM.
32 I/O pins, pin addressable (some are multiplexed) in 4 x 8 bit port usage.
Serial I/O: Two SFRs (SCON, SBUF) are used to control the programmable serial port, which is a full/duplex UART.
1. 8K is 213 so we need 13 address lines.
2. Memory is decoded with '0' active, so we use A13 '0' to CE/. This enables addresses (0000-1FFF) using address lines A0-A12.
3. If A13 goes high addresses (2000-3FFF) become active for the RAM 6164 CS. This CS is active high and therefore only decoded for A13='1'
4. PPI is decoded with A13 active low. It is therefore mutually excluded from RAM but not so with ROM.
5. The PPI is internallydecoded with A1,A2 for programming registers.
Potentially there is a problem in that one could read from ROM and think that they are reading a PPI port.
To solve this, PSEN/ is only active for ExternalROM access.
It can therefore be used with A13 to disable the PPI, as shown above
1. data/Address multiplexed 5 interrupt sources, each can be individually enabled/disabled.2. Each can be globally enabled/disabled3. Each is vectored to an individual address: Vectoring locates the ISR4. Each can be assigned one of two interrupt levels5. Nesting is possible to two levels6. External interrupts can be level or edge triggered.
#include <reg51.h>void main(void)
TMOD=0x01; /* 16-bit timer counter*/TH0=~(1000/256); /* quotient*/TL0=-(1000%256); /* remainder*/TR0=1; /* timer on*/}Counting up to 1000d at 12 Mhz (FFFFh-999d)= FC18hCounting up from FC18 to FFFF will be 999d. A further count up will reset counter to 000 which can be used to signal an interrupt to produce a real time clock.An interrupt occurs every 1 ms in order to allow processor to do other taks ie multitasking.We need to set up the interrupt SFR to signal am interrupt when the counter resets.Intrerrupt 1 is the timer 0 vector at 0BhInterrupt 3 -----||------------------ 1BhThe ISRs have to be located at these vectors
Q 2. Draw a diagram showing how an 8031, ROM-less chip can be interfaced to a memory expansion comprising a 16K EPROM and an 8K RAM and also an 8255 Programmable peripheral interface. Also draw the relevant timing waveforms and explain in detail how the full expansion functions.