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EE434 ASIC & Digital Systems

EE434 ASIC & Digital Systems. Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu. Test Methodologies. Adopted from “Essentials of Electronic Testing” by Bushnell and Agrawal. Lecture 26. Design for Testability (DFT): Partial-Scan & Scan Variations. Definition

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EE434 ASIC & Digital Systems

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  1. EE434ASIC & Digital Systems Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu

  2. Test Methodologies Adopted from “Essentials of Electronic Testing” by Bushnell and Agrawal Lecture 26

  3. Design for Testability (DFT): Partial-Scan & Scan Variations • Definition • Partial-scan architecture • Random-access scan (RAS) • Scan-hold flip-flop (SHFF) • Boundary scan • Summary

  4. Partial-Scan Definition • A subset of flip-flops is scanned. • Objectives: • Minimize area overhead and scan sequence length, yet achieve required fault coverage • Exclude selected flip-flops from scan: • Improve performance • Allow limited scan design rule violations • Allow automation: • In scan flip-flop selection • In test generation • Shorter scan sequences

  5. Partial-Scan Architecture PI PO Combinational circuit CK1 FF FF CK2 SCANOUT SFF TC SFF SCANIN

  6. Use of Gated Clock

  7. Using the System clock

  8. Flip-flop for Partial Scan • Normal scan flip-flop (SFF) with multiplexer of the LSSD flip-flop is used. • Scan flip-flops require a separate clock control: • Either use a separate clock pin • Or use an alternative design for a single clock pin D Master latch Slave latch MUX Q SD TC SFF (Scan flip-flop) CK TC CK Normal mode Scan mode

  9. Scan-Hold Flip-Flop (SHFF) To SD of next SHFF D • The control input HOLD keeps the output steady at previous state of flip-flop. • In the normal mode, TC=HOLD=1. In the scan mode, TC=1 and HOLD=0. This isolates the combinational logic from the scan register activity. • The state inputs of combinational logic driven by the hold latch remain frozen at their pre-scan value • Power Savings Q SD SFF TC Q CK HOLD

  10. Random-Access Scan (RAS) PI PO Combinational logic RAM nff bits CK TC SCANOUT SCANIN SEL Address decoder Address scan register log2 nff bits ADDRESS ACK

  11. RAS • All flip-flops form a RAM in the scan mode • In the normal mode, all flip-flops receive data from the combinational logic under the control of the clock CK • Flip-flop outputs directly feed into the combinational logic • Number of bits in flip-flop address = log nff • The address is loaded into an address scan register (ASR) using an address clock ACK • The address decoder now produces the select signal SEL=1 for the addressed flip-flop • For scanning data into a flip-flop, the scan mode is used

  12. RAS Flip-Flop (RAM Cell) D Q To comb. logic From comb. logic SD Scan flip-flop (SFF) SCANIN CK TC SCANOUT SEL

  13. RAS Applications • Logic test: • Reduced test length • Reduced scan power • Advantage: RAS may be suitable for certain architecture, e.g., where memory is implemented as a RAM block. • Disadvantages: • Not suitable for random logic architecture • High overhead – gates added to SFF, address decoder, address register, extra pins and routing

  14. Boundary Scan (BS)IEEE 1149.1 Standard • Developed for testing chips on a printed circuit board (PCB). • A chip with BS can be accessed for test from the edge connector of PCB. • BS hardware added to chip: • Test Access port (TAP) added • Four test pins • A test controller FSM • A scan flip-flop added to each I/O pin. • Standard is also known as JTAG (Joint Test Action Group) standard.

  15. System Test Logic

  16. System Configuration • Each pin of the chip has a register at that position • Serial connection of this register – boundary register • TDI – Serial input • TDO – Serial output • A number of registers can be connected between TDI and TDO

  17. Instruction Register Loading with JTAG

  18. System View of Interconnect

  19. Elementary Boundary Scan Cell

  20. Serial Board / MCM Scan

  21. Parallel Board / MCM Scan

  22. Independent Path Board / MCM Scan

  23. Tap Controller Signals • Test Access Port (TAP) includes these signals: • Test Clock Input(TCK) -- Clock for test logic • Can run at different rate from system clock • Test Mode Select(TMS) -- Switches system from functional to test mode • Test Data Input(TDI) -- Accepts serial test data and instructions -- used to shift in vectors or one of many test instructions • Test Data Output(TDO) -- Serially shifts out test results captured in boundary scan chain (or device ID or other internal registers) • Test Reset(TRST) -- Optional asynchronous TAP controller reset

  24. Tap Controller State Diagram

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