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R. Sethuram rms@qualcomm M. L. Bushnell bushnell@caip.rutgers V. D. Agrawal

Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. R. Sethuram rms@qualcomm.com M. L. Bushnell bushnell@caip.rutgers.edu V. D. Agrawal vagrawal@eng.auburn.edu. Outline. Purpose Introduction Terms and definitions

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R. Sethuram rms@qualcomm M. L. Bushnell bushnell@caip.rutgers V. D. Agrawal

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  1. Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults R. Sethuram rms@qualcomm.com M. L. Bushnell bushnell@caip.rutgers.edu V. D. Agrawal vagrawal@eng.auburn.edu

  2. Outline • Purpose • Introduction • Terms and definitions • Implication Graph • The New Functional Fault graph (FFG) • Identify Equivalence/Dominance/Independence and redundant faults using FFG • Results and analysis • Conclusion

  3. Purpose • Fault collapsing • Reducing ATPG Time • Test data volume • Identifying independent faults • Compaction • Extension for other fault models • Polynomial-time complexity

  4. Definitions • Fault dominance • f1 dominates f2 if every test of f2 detects f1 • Fault equivalence • If f1 and f2 dominate each other • Fault independence • If every test of f1 does not detect f2

  5. Implication Graph (IG) example • Graph represents Boolean expressions • Nodes represent literals, edges represent implications 1 3 2 1 3 2 1 3 2

  6. Operations on IG • Transitive Closure: adds an edge • For every path • For every common ancestor • Graph condensation 2 5 4 1 3 Strongly Connected Component (SCC) c a e b C1 C3 Condense d g f C2 C4

  7. Functional Fault Graphs (FFG) • New fault node to represent the fault detectability status a sa0 a c b a0 a a Oa Complete FFG of a 2-input AND gate

  8. Deriving Information • Perform transitive closure and graph condensation. Then, identify: • Equivalence: Fault nodes f1, f2, …, fk are in one SCC • Dominance: • Independence: • Untestable faults: f1 f2 f1 f2 f1 f1

  9. IGs are incomplete • Observability relationship between stem and its branches cannot be represented • It can be partially overcome If pand qare two signals such that q is the dominator of p then OpOq p q

  10. An example – i0 dominates d1 a c j h d g m e i k b f 1. d1OdOgOm and d1Odb 2. d1aj and d1a I 3. Om jOk and Ok bOi. Hence, d1Oi 4. d1i and d1Oi. Hence, d1 i0

  11. Extending for other Fault Models • Adding special nodes and edges in IG enables extending them for other fault models • Time frame edges for implication across time frames • Edges annotated with multiple bits -1 l lSR lSR 01 lSR 01 = Slow to raise fault 01 +1 01 Ol l Ol

  12. Results – Fault Collapsing # Dominant Faults • c6288 has several stems and our technique could not identify additional • observability related implications.

  13. Results – Comparison using the circuit c1355 # Dominant Faults

  14. Results - Independent fault pairs for c432

  15. Results – Untestable delay faults # Transition Delay Faults * Only the first K levels of the netlist were analyzed

  16. Conclusion • Proposed and implemented a functional fault graph for equivalence/dominance fault collapsing and identifying independent fault pairs • Requires only polynomial-time algorithms • Can be easily enhanced for other fault models • Reduces fault set size by up to 66%

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