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How to Improve Usability of WCET tools Dr.-Ing. Christian Ferdinand

How to Improve Usability of WCET tools Dr.-Ing. Christian Ferdinand AbsInt Angewandte Informatik GmbH. The Timing Problem. Unsafe: execution time measurement. Safe worst-case execution time estimate. Probability. Best-case execution time. Exact worst-case execution time. Execution time.

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How to Improve Usability of WCET tools Dr.-Ing. Christian Ferdinand

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  1. How to Improve Usability of WCET tools Dr.-Ing. Christian Ferdinand AbsInt Angewandte Informatik GmbH

  2. The Timing Problem Unsafe:execution timemeasurement Safe worst-caseexecution timeestimate Probability Best-caseexecution time Exact worst-caseexecution time Execution time

  3. aiT WCET Analyzer • The solution to the timing problem • Global program analysis • abstract interpretation for cache, pipeline, and value analysis • integer linear programming for path analysis • Everything combined in a single intuitive GUI

  4. aiT WCET Analyzer Structure Executable program CFG builder AIS file Loop trafo CRL file CRL file Static analyses Path analysis Loop/value analyzer ILP generator LP solver Cache/pipelineanalyzer Evaluation WCET,visualization

  5. aiT WCET Analysis Input/Output Application Code void Task (void) { variable++; function(); next++: if (next) do this; terminate() } clock 10200 kHz ; loop "_codebook" + 1 loop exactly 16 end ; recursion "_fac" max 6; SNIPPET "printf" IS NOT ANALYZED AND TAKES MAX 333 CYCLES; flow "U_MOD" + 0xAC bytes / "U_MOD" + 0xC4 bytes is max 4; area from 0x20 to 0x497 is read-only; aiT Entry Point Compiler Linker Executable (*.elf / *.out) à =€@€ aŒ† | @€,@€;ÞKÿÿô;ÿ Kÿÿ؉€2}Œ`øÿÿ™€(8H#鳡¶€( Specifications (*.ais) • Worst Case Execution Time • Visualization, Documentation

  6. Correctness of Pipeline ModelsDerivation of Pipeline Models from VHDL Specifications

  7. Integration into the Development Chain:SCADE / aiT automated Flow

  8. Integration into the Development Chain: Analysis Reports • Customizable HTML reports • Global and detailed reports • Diff feature

  9. System model(tasks, activation,scheduling) WCET/stack analysis (single task) Scheduling analysis (WCRT)system stack analysis Integration into the Development Chain: Scheduling Analysis Tools System level:SymTA/S / RT-Druid Code level:aiT/StackAnalyzer Additional info WCET/stack request Refinement WCET/stack response

  10. Integration into the Development Chain: INTEREST Demonstrator: Engine Control System on TriCore 1796 (Ascet, SymTA/S, aiT)

  11. Exploration During Early Design PhasesTimingExplorer void Task (void) { variable++; function(); while (next) { do this; next--; } terminate(); } T1 WCET T1 T2 Source files

  12. Reduce the Amount of AnnotationsSource-Level Analyses • Source-level analyses to automatically generate AIS-annotations • SWEET from Mälardalen University • SATIRE from TU Vienna • Upper bounds of loop iterations • Targets of indirect function calls • Mutually exclusive program part • Optimizing compilers require inspection of the binary code

  13. Reduce the Amount of AnnotationsSource-Level Analysis:Automatic Mode Detection • A mode of an application is usually characterized by the values of a set of variables • The mode variables determine the control flow of the application • The mode variables usually do not change during the execution • Source-level analysis to automatically detect application mode variables and values • Implemented with SATIRE

  14. Summary • Safe deviation of pipeline models • Integrations with model-based development tools • Interface to scheduling analysis tools • Support to reduce the amount of annotations • New application areas • Software integration • Architecture exploration

  15. Research Projects

  16. Contact www.absint.com info@absint.com

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