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Nanotechnology: Spatial Computing Using Molecular Electronics. Mihai Budiu joint work with Seth Copen Goldstein Dan Rosewater. Nanotechnology. Computer architecture. Intersection of Three Areas. Reconfigurable computing. Prophecies, A Risky Endeavor.

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Nanotechnology: Spatial Computing Using Molecular Electronics

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Nanotechnology spatial computing using molecular electronics l.jpg

Nanotechnology: Spatial Computing Using Molecular Electronics

Mihai Budiu

joint work with

Seth Copen Goldstein

Dan Rosewater


Intersection of three areas l.jpg

Nanotechnology

Computer

architecture

Intersection of Three Areas

Reconfigurable

computing


Prophecies a risky endeavor l.jpg

Prophecies, A Risky Endeavor

There is no reason anyone would want a computer in their home.

--- Ken Olson

I think there is a world market for maybe five computers.

--- T. J. Watson

There is not the slightest indication that nuclear energy will ever be obtainable.

--- Albert Einstein

640K ought to be enough for everybody.

--- Bill Gates

I will propose this semester.

--- Anonymous


Moore s law l.jpg

Moore’s Law


Moore s second law l.jpg

Moore’s Second Law

X 1000$

generation

Plant cost

Mask cost


Our proposal l.jpg

Our Proposal

  • Nanotechnology

  • cheap

  • high-density

  • low-power

  • unreliable

  • Reconfigurable

  • Computing

  • defect tolerant

  • high performance

  • low density

_

+

+

+

_

+

+

_

+

_

  • Computer architecture

  • vast body of knowledge

  • expensive

  • high-power


Paradigm shift l.jpg

Paradigm Shift

Configuration

Executable

Dense, regular structure

+

Configuration

Complex fixed chip

+

Program


Outline l.jpg

Outline

  • Introduction

  • Reconfigurable computing

  • Nanotechnology

  • Nano-architecture proposal

  • Preliminary results

  • Conclusions and Future Work


Reconfigurable computing l.jpg

Reconfigurable Computing

  • Back to ENIAC-style computing

  • Synthesize one machine to solve one problem


Island style rc architecture l.jpg

Interconnection

network

Universal gates

and/or

storage elements

Programmable Switches

Island-Style RC Architecture


Main rc ingredient ram cell l.jpg

Main RC Ingredient: RAM Cell

0

0

0

1

a0

data

a0

a1 & a2

a1

a1

Universal gate = RAM

data in

0

control

Switch controlled by a 1-bit RAM cell


Place and route l.jpg

Place and Route

int reverse(int x)

{

int k,r=0;

for (k=0; k<64; k++)

r |= x&1;

x = x >> 1;

r = r << 1;

}

}

int func(int* a,int *b)

{

int j,sum=0;

for (j=0; *a>0; j++)

sum+=reverse(*b


Kernel speedup using piperench l.jpg

1000

189.7

100

63.3

57.1

42.4

29.0

26.0

15.5

12.0

11.3

10

1

FIR

ATR

DCT

Over

IDEA

Cordic

DCT-2D

Nqueens

PopCount

Kernel Speedup Using PipeRench

Times Over 300Mhz UltraSparc-II


Defect tolerance l.jpg

Defect Tolerance

  • Despite having >70% of the chips defective, Teramac works flawlessly.

  • Compilation has two phases:

  • defect detection through self-testing

  • placement for defect-avoidance


Outline15 l.jpg

Outline

  • Introduction

  • Reconfigurable computing

  • Nanotechnology

  • Nano-architecture proposal

  • Preliminary results

  • Conclusions and Future work


Nanotechnology l.jpg

Nanotechnology


Predicted features l.jpg

Predicted Features

  • Low Power: 1010 gates use less than 2 W

    (compare to 3x107 transistors using 100 W in CMOS)

  • Low cost

    (nanocents/gate)

  • Small size

    (105 factor area gain)

Nano-RAM cell

.

In yellow: a CMOS RAM cell


Nano wires l.jpg

Nano-wires

  • carbon nanotubues, Si, metal

  • >2nm diameter, up to mm length

  • excellent electrical properties

A carbon nanotube: one molecule


Nano switch l.jpg

Nano-switch


Nano switch between nano wires l.jpg

Nano-switch Between Nano-wires


Self assembly l.jpg

Self-assembly


No complex irregular structures l.jpg

No Complex Irregular Structures


No three terminal devices l.jpg

No Three-Terminal Devices


Diode resistor logic l.jpg

V

DD

Output

Input 1

Input 2

Diode-resistor Logic

V

V

V

V

AND

AND

B

B

A

A

A

B

A * B

A ^ B

A * B

Nano-implementation

Electrical equivalent


Nanoscale latches l.jpg

Nanoscale Latches

  • Provide:

  • signal restoration (amplification)

  • clocking (synchronization)

  • memory

data

out

D

clock


High defect rate l.jpg

High Defect Rate


Outline27 l.jpg

Outline

  • Introduction

  • Reconfigurable computing

  • Nanotechnology

  • Nano-architecture proposal

  • Preliminary results

  • Conclusions and future work


The nanoblock 3 in to 3 out logic l.jpg

The nanoBlock (3-in to 3-out Logic)

CMOS

Inputs

+Vdd

clk

Gnd

Gnd

clk

Outputs


Interconnecting nanoblocks l.jpg

Interconnecting nanoBlocks

Switch block


Global view l.jpg

Global View


Many clusters nanofabric l.jpg

Many Clusters = nanoFabric

Control

cluster

long-lines


Compilation l.jpg

Compilation

int reverse(int x){ int k,r=0; for (k=0; k<64; k++) r |= x&1; x = x >> 1; r = r << 1; }}

  • Program

  • Split-phase Abstract Machines

  • Configurations placed independently

  • Placement on chip

Computations

& local storage

Unknown latency ops.


Outline33 l.jpg

Outline

  • Introduction

  • Reconfigurable Hardware

  • Nanotechnology

  • Nano-architecture proposal

  • Preliminary results

  • Conclusions and Future work


A limit study of performance l.jpg

Control-flow transfer

Basic block

Memory write

Memory read

Memory word

A Limit Study of Performance

A graph of the whole program execution:


Area 10 6 units cm 2 available l.jpg

Area(106 units/cm2 available)


Typical program graph g721 e l.jpg

Typical Program Graph (g721_e)

Memory reads

Control flow transfer

100% code cluster

100% memory cluster


Typical program graph g721 e37 l.jpg

Typical Program Graph (g721_e)

Memory reads

Control flow transfer

code

memcpy

memory


Program graph after inlining memcpy l.jpg

Program Graph After Inlining memcpy

memcpy


Application slowdown l.jpg

Application Slowdown


How time is spent l.jpg

How Time Is Spent

No caches: reads expensive

No speculation


Future work l.jpg

Future Work

  • Better nano-devices

  • More accurate hardware models in simulations

  • Compilation technology


Conclusions l.jpg

Conclusions

  • Electronic nanotechnology promises to transcend the limitations of CMOS

  • Nanofabrics are very well suited to reconfigurable computation

  • 109-gate designs can be managed through hierarchies of abstract machines


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