Scaling Effects on MOSFET Parameters: An Analysis of CMOS Devices

1. The George Washington UniversitySchool of Engineering and Applied ScienceDepartment of Electrical and Computer Engineering ECE122 – Lab 7 MOSFET Parameters and Scaling Effects Jason Woytowich Ritu Bajpai Last revised on November 1, 2007

2. CMOS Scaling • Devices are constantly shrinking in an effort to increase the number of devices on a chip. • The state-of-the-art mass production is moving into ~65nm. • Clock speeds are scaled up to increase performance.

3. Effects on the device • Short-channel effects on VT: If we reduce the channel length beyond a certain limit the source and drain depletion regions begin to affect the threshold voltage. • Velocity saturation: With devices getting smaller they are exposed to high electric fields leading to drift velocity reaching its upper bound.

4. Effects on the device • Gate leakage current (IG):The gate dielectric is needed to prevent charge from passing from the gate to channel of a MOSFET. All insulators, when sufficiently thin, allow some electrons, and thus some current, to pass through due to quantum mechanical effects.

5. Effects on the device • Sub threshold current (ID): This is the current flowing through the transistor when it is nominally off (Ioff). Ideally we want this current to be low. But like Ion it is also proportional to (VGS-VT).

6. Effects on the circuit • Decreased supply voltage: As supply voltage is reduced, the charge stored will be small. With larger subthreshold leakage current, coupling noise etc is will be a challenge to get circuits to operate properly. • Increased role of wiring resistance, inductance and capacitance.

7. Effects on the circuit • Interconnect coupling: Wires are getting thinner but not decreasing as rapidly in height. This makes them look like tall thin conductors which form parallel plate capacitors. • IR Drop: Narrow wires have a non negligible resistance. • Electromigration: This involves migration of metal molecules due to high current densities and narrow line widths leading to a short or open in the metal line.

8. Spice MODELS • The standard spice model is not sufficient to capture all of these effects. • There have been many upgrades to it in order to increase it’s effectiveness.

9. Review of Spice Parameters .model nmos nmos Level=1 + Vto=1.0 Kp=3.0E-5 Gamma=0.35 + Phi=0.65 Lambda=0.02 Tox=0.1u + Nsub=1.0E+15 Nss=1.0E+10 Ld=0.01u + Tpg=1.00 Uo=700.0 Af=1.2 + Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8 + Pb=0.75 Cj=2.0E-4 Mj=0.5 + Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5 + Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11 + Rd=10.0 Rs=10.0 Rsh=30.0

10. The “REAL” Data • http://www.mosis.org/cgi-bin/cgiwrap/umosis/swp/params/ibm-018/t67j_7wl_5lm_ma-params.txt file will serve as the real data • Save the above file as .md file. • Make changes so as to correspond to the tanner .md format.

11. The test setup

12. The simulation • A DC sweep of 100 points of VDS from 0 to 1.8V • A Secondary sweep of 10 points of VGS from 0 to 1.8V .dc source VDS lin 100 0 1.8 sweep source VGS lin 10 0 1.8 .include "C:\Documents and Settings\Student\Desktop\ECE122_Lab7\ml1_typ.md“ *replace with your path name *.include "C:\Documents and Settings\Student\Desktop\ECE122_Lab7\IBM_018u.md“// put your pathname .print dc i(M1,D) * Main circuit: MosfetTest M1 D G Gnd Gnd NMOS L=180n W=1u AD=66p PD=24u AS=66p PS=24u VGS G Gnd 5.0 VDS D Gnd 5.0 * End of main circuit: MosfetTest

15. Analysis and Results • Show the ID vs. VDS characteristic for the spice level 1 and for the Mosis transistor data. • Why do you think the two characteristic curves are different?