Digital design principles and practices
This presentation is the property of its rightful owner.
Sponsored Links
1 / 26

Digital Design: Principles and Practices PowerPoint PPT Presentation


  • 102 Views
  • Uploaded on
  • Presentation posted in: General

Digital Design: Principles and Practices. Chapter 9 Memory, CPLDs, and FPGAs. 9.1 Read-Only Memory. Read-Only Memory (ROM). A read-only memory ( ROM ) is a combinational circuit with n inputs and b outputs.

Download Presentation

Digital Design: Principles and Practices

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Digital design principles and practices

Digital Design:Principles and Practices

Chapter 9

Memory, CPLDs, and FPGAs


9 1 read only memory

9.1 Read-Only Memory


Read only memory rom

Read-Only Memory (ROM)

  • A read-only memory (ROM) is a combinational circuit with n inputs and b outputs.

    • The inputs are called address inputs and are traditionally named A0, A1, …, An-1.

    • The outputs are called data outputs and are typically named D0, D1, …, Db-1.


Read only memory rom1

Read-Only Memory (ROM)

  • A ROM “stores” the truth table of an n-input, b-output combinational logic function.


Read only memory rom2

Read-Only Memory (ROM)

  • A ROM is a combinational circuit

    • Not really a memory

    • Information is “stored” when a ROM is manufactured or programmed.

  • ROM is nonvolatile memory; that is, its contents are preserved even if no power is applied.


Nonvolatile memory

Nonvolatile Memory

  • ROM: hardwired during fabrication

  • PROM (programmable ROM): can be programmed once only

    • fuse

  • EPROM (Erasable PROM): can be erased by UV light, and can be re-programmed

    • Floating gate

  • EEPROM (Electrically Erasable PROM): can be erased with on-chip circuitry

    • Floating gate

  • Flash memory: a variant of EEPROM that erases entire blocks rather than individual bits

    • Floating gate


Categories of memory arrays

Categories of Memory Arrays


Programmable roms

Programmable ROMs

  • ROM has in practice become synonymous with nonvolatile, not read-only memory.

  • Programming/writing speeds are generally slower than read speeds.

  • Four type of nonvolatile memories:

    • PROM (Programmable ROM)

    • EPROM (Erasable Programmable ROM)

    • EEPROM (Electrically Erasable Programmable ROM)

    • Flash memories

  • PROMs us fuses while EPROMs, EEPROMs, and Flash use charge stored on a floating gate.


Floating gate nmos transistor

Floating Gate nMOS Transistor


Floating gate nmos transistor1

Floating Gate nMOS Transistor

  • The floating gate is a good conductor, but it is not attached to anything.

  • Applying a high voltage to the upper gate causes electrons to jump through the thin oxide onto the floating gate.

  • Injecting the electrons induces a negative voltage on the floating gate, effectively increasing the threshold voltage (Vt) of the transistor to the point that it is always OFF.

  • EPROM: knock off the electrons off the floating gate by UV light

  • EEPROM and Flash can be erased electrically.


9 2 read write memory

9.2 Read/Write Memory


Read write memory

Read/Write Memory

  • The name read/write memory (RWM) is given to memory arrays in which we can store and retrieve information at any time.

  • Random-Access Memory (RAM)

    • Static RAM (SRAM)

    • Dynamic RAM (DRAM)


9 3 static ram

9.3 Static RAM


Basic structure of a 2 n x b ram

Basic Structure of a 2n x b RAM

  • CS: Chip Select

  • OE: Output Enable

  • WE: Write Enable

  • Read: CS and OE are asserted

  • Write: CS and WE are asserted


Internal structure of an 8 x 4 sram

Internal Structure of an 8 x 4 SRAM


Functional behavior of an sram cell

Functional Behavior of an SRAM Cell


12 transistor sram cell

12-Transistor SRAM Cell


6 transistor 6t sram cell

6-Transistor (6T) SRAM Cell


Stick diagram of 6t sram cell

Stick Diagram of 6T SRAM Cell


Layout of 6t sram cell

Layout of 6T SRAM Cell

Only poly and diff layers are shown.


9 4 dynamic ram

9.4 Dynamic RAM


Dram cell

DRAM Cell


Dram cell1

DRAM Cell

  • A DRAM cell contains a transistor and a capacitor.

  • A basic DRAM cell is substantially smaller than a SRAM cell, but the cell must be periodically read and refreshed so that its contents do not leak away.

  • One a read, the bitline is first precharged to VDD/2. When the wordline rises, the capacitor shares its charge with the bitline, causing a voltage change △V that can be sensed. The read process disturbs the cell contents at x, so the cell must be rewritten after each read. [Figure 11.26]

    • Sense amplifier


Dram cell read operation

DRAM Cell – Read Operation


Dram s capacitor

DRAM’s Capacitor


Dram s capacitor1

DRAM’s Capacitor

  • A large cell capacitance (Ccell) is important to provide a reasonable voltage swing. It also is necessary to retain the contents of the cell for an acceptably long time.

  • Specialized DRAM processes are required for manufacturing trench capacitors.


  • Login