An empirical evaluation of semiconductor file memory as a disk cache
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An Empirical Evaluation of Semiconductor File Memory as a Disk Cache. John C. Koob Duncan G. Elliott Bruce F. Cockburn VLSI Design Lab ECE Department University of Alberta Edmonton, Alberta Canada. Outline. Motivation Extended Storage File Memory Experimental Platform

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An Empirical Evaluation of Semiconductor File Memory as a Disk Cache

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An empirical evaluation of semiconductor file memory as a disk cache

An Empirical Evaluation of SemiconductorFile Memory as a Disk Cache

John C. Koob

Duncan G. Elliott

Bruce F. Cockburn

VLSI Design Lab

ECE Department

University of Alberta

Edmonton, Alberta

Canada


Outline

Outline

  • Motivation

  • Extended Storage

  • File Memory

  • Experimental Platform

  • Cost/Performance Analysis

  • Conclusions


Motivation

Motivation

Source: Computer Architecture, Hennessy & Patterson, 2003


Access time gap problem

Access Time Gap Problem

  • Use Extended Storage

    • Cheaper per bit than main memory

    • Faster than disk

    • Slower than main memory

    • Potential for power savings

  • How to fill the access time gap?


Historical systems

Historical Systems

  • Extended storage first appeared in expensive systems

    • IBM 3090mainframe

      • Main memory: 0.5 GB

      • Extended storage: 4 GB

      • Terminology: Expanded Storage

Image courtesy of www.ibm.com


Historical systems1

Historical Systems

  • Extended storage first appeared in expensive systems

    • Cray Y-MPsupercomputer

      • Main memory: 1 GB of 15-ns SRAM

      • Extended storage: 4 GB of 50-ns DRAM

      • Terminology: Solid State Disk

Image courtesy of the Charles Babbage Institute


Recent research

Recent Research

  • Compressed caching (1999-2003)

    • Compression can reduce paging costs

    • Adaptive sizing of compressed page cache

  • Multi-level main memory (WMPI 2004)

    • 30% of memory must run at DRAM speed

    • Remaining memory can be slower


Extended storage today

Extended Storage Today?

  • Emerging technology may prompt

    a return to extended storage

    • Semiconductor file memory

      • Up to 5 times slower than DRAM

      • Cheaper per bit than DRAM

    • MEMS probe-based storage

      • 5 times faster than disk

      • 10 times more expensive than disk


What is file memory

What is File Memory?

  • File memory leverages current DRAM technology

    • DRAM design constraints increase costs per bit

      • 100% of nominal capacity must be functional

      • Contiguous address space

    • File memory relaxes DRAM’s design constraints

      • Bad block marking to improve yield

      • Address space is not contiguous

      • Improve density at the expense of performance

        (e.g. multi-level DRAM or hardware compression)


Feasibility of file memory

Contiguous Memory

Non-Contiguous Memory

Feasibility of File Memory

  • A precedent for file memory exists

    in the non-volatile memory market

    • NOR Flash memory

      • Limited capacity

      • Moderate reliability

      • Random-access supported

  • NAND Flash memory

    • High capacity

    • Low reliability  bad block marking

    • Restricted to sequential access


Extended storage disk cache

Extended Storage Disk Cache

  • To evaluate file memory as extended storage:

    • Require an experimental platform

    • Modify Linux 2.4.18 OS kernel

  • ESDC Design Summary

    • High memory support

    • Page cache containment

    • Configurable performance

    • CPU caching issues

    • Performance metrics


Postmark results using file memory

Postmark Results using File Memory


Postmark results analysis

Postmark Results Analysis

Need 39% more file memory for equivalent performance


Summary of postmark results

Summary of Postmark Results


Conclusions

Conclusions

  • Use file memory for extended storage

    • Leverage DRAM cell technology

    • Relax DRAM design constraints

    • Use bad block marking

  • Preliminary evaluation of ESDC

    • File memory can be up to 4 times slower than DRAM

    • Performance improved even with no page cache

  • Ongoing research

    • Evaluate hierarchies with file memory and page cache


Selected references

Selected References

Bray. Bonnie. www.textuality.com/bonnie, 1996.

Castro et al. Adaptive compressed caching. Symp. on Comp. Arch. And High Performance Computing, Nov. 2003.

Ekman and Stenstrom. A case for multi-level main memory. WMPI 2004.

Hennessy and Patterson. Computer architecture: A quantitative approach. Third Edition, 2003.

Katcher. PostMark: A new filesystem benchmark. TR3022, Network Appliance, Oct. 1997.

Koob et al. Test and characterization of a variable capacity multilevel DRAM. In Proc. VLSI Test Symp., pp. 189-197, May 2005.

Uysal et al. Using MEMS-based storage in disk arrays. FAST 2003, pp. 89-101.


Configurable performance

Configurable Performance

  • How to model different file memory access times?

    • Use multiple page copies

    • Gives accurate file memory slowdown ratios

    • Problem:

      • Repeated page copies would be cached

    • Solution:

      • Disable CPU caches for ESDC

        • Use IA-32 memory type range registers (MTRRs)


Experimental setup

Experimental Setup

  • Experimental Platform

    • Processor 2.4 GHz Pentium 4

    • Memory2 GB DDR SDRAM

    • Hard disk18-GB Seagate SCSI

    • Disk buffer4-MB

  • Experimental Suite

    • PostMark – benchmark for many small files

    • Bonnie – file system benchmark

    • Kernel compilation – Linux kernel build


Postmark results for original hierarchy

Postmark Results for Original Hierarchy


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